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Searched refs:PIPESTAT (Results 1 – 5 of 5) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Di915_irq.c369 u32 reg = PIPESTAT(pipe); in __i915_enable_pipestat()
396 u32 reg = PIPESTAT(pipe); in __i915_disable_pipestat()
1711 reg = PIPESTAT(pipe); in valleyview_pipestat_irq_handler()
2454 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); in i915_report_and_clear_eir()
3051 I915_WRITE(PIPESTAT(pipe), 0xffff); in vlv_display_irq_reset()
3286 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_install()
3287 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_install()
3340 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_uninstall()
3341 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_uninstall()
3576 I915_WRITE(PIPESTAT(pipe), 0); in i8xx_irq_preinstall()
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Dintel_fifo_underrun.c102 u32 reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
126 u32 reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()
Di915_debugfs.c736 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
823 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
859 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
Di915_reg.h4042 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) macro
Dintel_display.c14531 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()