Searched refs:PIPECONF (Results 1 – 5 of 5) sorted by relevance
1029 int reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()1310 reg = PIPECONF(cpu_transcoder); in assert_pipe()1973 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()2017 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()2124 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()2162 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()3642 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()3740 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()4038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()[all …]
565 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
609 dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & in intel_dsi_get_hw_state()
4038 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) macro
5054 reg = PIPECONF(intel_crtc->config->cpu_transcoder); in intel_dp_set_drrs_state()