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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 7 of 7) sorted by relevance

/linux-4.1.27/drivers/pinctrl/sh-pfc/
Dpfc-r8a7791.c5292 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5351 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5387 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5423 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5461 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5503 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5541 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5581 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5622 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5665 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7778.c2279 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2334 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2377 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2429 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2471 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2513 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2557 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2608 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2647 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2687 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-sh7734.c1833 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1870 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1905 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1941 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1978 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2013 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2053 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2097 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2133 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2169 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
[all …]
Dpfc-emev2.c1594 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1612 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1624 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1636 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1661 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1680 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
Dpfc-r8a7790.c4854 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4890 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4927 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4956 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4989 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5022 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5059 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5095 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5130 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5171 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7779.c3240 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3278 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3316 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3362 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3413 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3461 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3507 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3544 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3580 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3623 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dsh_pfc.h82 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro
309 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\