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Searched refs:PHY_CONTROL (Results 1 – 7 of 7) sorted by relevance

/linux-4.1.27/Documentation/devicetree/bindings/usb/
Dsamsung-usbphy.txt37 - reg : base physical address of PHY_CONTROL registers.
38 The size of this register is the total sum of size of all PHY_CONTROL
40 '0x4' in case we have only one PHY_CONTROL register (e.g.
42 and, '0x8' in case we have two PHY_CONTROL registers (e.g.
60 /* USB device and host PHY_CONTROL registers */
93 - reg : base physical address of PHY_CONTROL registers.
94 The size of this register is the total sum of size of all PHY_CONTROL
96 '0x4' in case we have only one PHY_CONTROL register (e.g.
98 and, '0x8' in case we have two PHY_CONTROL registers (e.g.
114 /* USB device and host PHY_CONTROL registers */
/linux-4.1.27/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c27 #define PHY_CONTROL 0x00 /* Control Register */ macro
191 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &phy_ctrl); in pch_gbe_phy_sw_reset()
193 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, phy_ctrl); in pch_gbe_phy_sw_reset()
203 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, PHY_CONTROL_DEFAULT); in pch_gbe_phy_hw_reset()
225 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); in pch_gbe_phy_power_up()
227 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); in pch_gbe_phy_power_up()
244 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); in pch_gbe_phy_power_down()
246 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); in pch_gbe_phy_power_down()
/linux-4.1.27/drivers/net/ethernet/intel/igb/
De1000_phy.c909 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); in igb_copper_link_autoneg()
914 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); in igb_copper_link_autoneg()
1159 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); in igb_phy_force_speed_duplex_igp()
1165 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); in igb_phy_force_speed_duplex_igp()
1243 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); in igb_phy_force_speed_duplex_m88()
1249 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); in igb_phy_force_speed_duplex_m88()
2055 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); in igb_phy_sw_reset()
2060 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); in igb_phy_sw_reset()
2209 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igb_power_up_phy_copper()
2211 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); in igb_power_up_phy_copper()
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De1000_defines.h670 #define PHY_CONTROL 0x00 /* Control Register */ macro
Digb_ethtool.c1609 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); in igb_integrated_phy_loopback()
1611 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); in igb_integrated_phy_loopback()
1615 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); in igb_integrated_phy_loopback()
1626 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); in igb_integrated_phy_loopback()
1756 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); in igb_loopback_cleanup()
1759 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); in igb_loopback_cleanup()
/linux-4.1.27/drivers/net/ethernet/apm/xgene/
Dxgene_enet_sgmac.h26 #define PHY_CONTROL(src) ((src) & GENMASK(15, 0)) macro
Dxgene_enet_sgmac.c158 wr_data = PHY_CONTROL(data); in xgene_mii_phy_write()