H A D | vb_init.c | 38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02; XGINew_GetXG20DRAMType() 40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) & XGINew_GetXG20DRAMType() 44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B); XGINew_GetXG20DRAMType() 75 static void XGINew_DDR1x_MRS_340(unsigned long P3c4, XGINew_DDR1x_MRS_340() argument 78 xgifb_reg_set(P3c4, 0x18, 0x01); XGINew_DDR1x_MRS_340() 79 xgifb_reg_set(P3c4, 0x19, 0x20); XGINew_DDR1x_MRS_340() 80 xgifb_reg_set(P3c4, 0x16, 0x00); XGINew_DDR1x_MRS_340() 81 xgifb_reg_set(P3c4, 0x16, 0x80); XGINew_DDR1x_MRS_340() 84 xgifb_reg_set(P3c4, 0x18, 0x00); XGINew_DDR1x_MRS_340() 85 xgifb_reg_set(P3c4, 0x19, 0x20); XGINew_DDR1x_MRS_340() 86 xgifb_reg_set(P3c4, 0x16, 0x00); XGINew_DDR1x_MRS_340() 87 xgifb_reg_set(P3c4, 0x16, 0x80); XGINew_DDR1x_MRS_340() 90 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ XGINew_DDR1x_MRS_340() 91 xgifb_reg_set(P3c4, 0x19, 0x01); XGINew_DDR1x_MRS_340() 92 xgifb_reg_set(P3c4, 0x16, 0x03); XGINew_DDR1x_MRS_340() 93 xgifb_reg_set(P3c4, 0x16, 0x83); XGINew_DDR1x_MRS_340() 95 xgifb_reg_set(P3c4, 0x1B, 0x03); XGINew_DDR1x_MRS_340() 97 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ XGINew_DDR1x_MRS_340() 98 xgifb_reg_set(P3c4, 0x19, 0x00); XGINew_DDR1x_MRS_340() 99 xgifb_reg_set(P3c4, 0x16, 0x03); XGINew_DDR1x_MRS_340() 100 xgifb_reg_set(P3c4, 0x16, 0x83); XGINew_DDR1x_MRS_340() 101 xgifb_reg_set(P3c4, 0x1B, 0x00); XGINew_DDR1x_MRS_340() 106 xgifb_reg_set(pVBInfo->P3c4, XGINew_SetMemoryClock() 109 xgifb_reg_set(pVBInfo->P3c4, XGINew_SetMemoryClock() 112 xgifb_reg_set(pVBInfo->P3c4, XGINew_SetMemoryClock() 116 xgifb_reg_set(pVBInfo->P3c4, XGINew_SetMemoryClock() 119 xgifb_reg_set(pVBInfo->P3c4, XGINew_SetMemoryClock() 122 xgifb_reg_set(pVBInfo->P3c4, XGINew_SetMemoryClock() 129 unsigned long P3c4, struct vb_device_info *pVBInfo) XGINew_DDRII_Bootup_XG27() 131 unsigned long P3d4 = P3c4 + 0x10; XGINew_DDRII_Bootup_XG27() 141 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */ XGINew_DDRII_Bootup_XG27() 142 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */ XGINew_DDRII_Bootup_XG27() 143 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 145 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 148 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */ XGINew_DDRII_Bootup_XG27() 149 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */ XGINew_DDRII_Bootup_XG27() 150 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 152 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 155 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */ XGINew_DDRII_Bootup_XG27() 156 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */ XGINew_DDRII_Bootup_XG27() 157 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 159 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 162 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */ XGINew_DDRII_Bootup_XG27() 163 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */ XGINew_DDRII_Bootup_XG27() 164 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 166 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 167 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 169 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */ XGINew_DDRII_Bootup_XG27() 171 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */ XGINew_DDRII_Bootup_XG27() 173 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */ XGINew_DDRII_Bootup_XG27() 174 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */ XGINew_DDRII_Bootup_XG27() 175 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 178 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 181 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */ XGINew_DDRII_Bootup_XG27() 182 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */ XGINew_DDRII_Bootup_XG27() 183 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 185 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 188 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */ XGINew_DDRII_Bootup_XG27() 189 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */ XGINew_DDRII_Bootup_XG27() 190 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 192 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ XGINew_DDRII_Bootup_XG27() 196 xgifb_reg_set(P3c4, 0x1B, 0x04); XGINew_DDRII_Bootup_XG27() 202 unsigned long P3c4, struct vb_device_info *pVBInfo) XGINew_DDR2_MRS_XG20() 204 unsigned long P3d4 = P3c4 + 0x10; XGINew_DDR2_MRS_XG20() 212 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */ XGINew_DDR2_MRS_XG20() 213 xgifb_reg_set(P3c4, 0x19, 0x80); XGINew_DDR2_MRS_XG20() 214 xgifb_reg_set(P3c4, 0x16, 0x05); XGINew_DDR2_MRS_XG20() 215 xgifb_reg_set(P3c4, 0x16, 0x85); XGINew_DDR2_MRS_XG20() 217 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */ XGINew_DDR2_MRS_XG20() 218 xgifb_reg_set(P3c4, 0x19, 0xC0); XGINew_DDR2_MRS_XG20() 219 xgifb_reg_set(P3c4, 0x16, 0x05); XGINew_DDR2_MRS_XG20() 220 xgifb_reg_set(P3c4, 0x16, 0x85); XGINew_DDR2_MRS_XG20() 222 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */ XGINew_DDR2_MRS_XG20() 223 xgifb_reg_set(P3c4, 0x19, 0x40); XGINew_DDR2_MRS_XG20() 224 xgifb_reg_set(P3c4, 0x16, 0x05); XGINew_DDR2_MRS_XG20() 225 xgifb_reg_set(P3c4, 0x16, 0x85); XGINew_DDR2_MRS_XG20() 227 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */ XGINew_DDR2_MRS_XG20() 228 xgifb_reg_set(P3c4, 0x19, 0x02); XGINew_DDR2_MRS_XG20() 229 xgifb_reg_set(P3c4, 0x16, 0x05); XGINew_DDR2_MRS_XG20() 230 xgifb_reg_set(P3c4, 0x16, 0x85); XGINew_DDR2_MRS_XG20() 233 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */ XGINew_DDR2_MRS_XG20() 235 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */ XGINew_DDR2_MRS_XG20() 238 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */ XGINew_DDR2_MRS_XG20() 239 xgifb_reg_set(P3c4, 0x19, 0x00); XGINew_DDR2_MRS_XG20() 240 xgifb_reg_set(P3c4, 0x16, 0x05); XGINew_DDR2_MRS_XG20() 241 xgifb_reg_set(P3c4, 0x16, 0x85); XGINew_DDR2_MRS_XG20() 246 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, XGINew_DDR1x_MRS_XG20() argument 249 xgifb_reg_set(P3c4, 0x18, 0x01); XGINew_DDR1x_MRS_XG20() 250 xgifb_reg_set(P3c4, 0x19, 0x40); XGINew_DDR1x_MRS_XG20() 251 xgifb_reg_set(P3c4, 0x16, 0x00); XGINew_DDR1x_MRS_XG20() 252 xgifb_reg_set(P3c4, 0x16, 0x80); XGINew_DDR1x_MRS_XG20() 255 xgifb_reg_set(P3c4, 0x18, 0x00); XGINew_DDR1x_MRS_XG20() 256 xgifb_reg_set(P3c4, 0x19, 0x40); XGINew_DDR1x_MRS_XG20() 257 xgifb_reg_set(P3c4, 0x16, 0x00); XGINew_DDR1x_MRS_XG20() 258 xgifb_reg_set(P3c4, 0x16, 0x80); XGINew_DDR1x_MRS_XG20() 260 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ XGINew_DDR1x_MRS_XG20() 261 xgifb_reg_set(P3c4, 0x19, 0x01); XGINew_DDR1x_MRS_XG20() 262 xgifb_reg_set(P3c4, 0x16, 0x03); XGINew_DDR1x_MRS_XG20() 263 xgifb_reg_set(P3c4, 0x16, 0x83); XGINew_DDR1x_MRS_XG20() 265 xgifb_reg_set(P3c4, 0x1B, 0x03); XGINew_DDR1x_MRS_XG20() 267 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ XGINew_DDR1x_MRS_XG20() 268 xgifb_reg_set(P3c4, 0x19, 0x00); XGINew_DDR1x_MRS_XG20() 269 xgifb_reg_set(P3c4, 0x16, 0x03); XGINew_DDR1x_MRS_XG20() 270 xgifb_reg_set(P3c4, 0x16, 0x83); XGINew_DDR1x_MRS_XG20() 271 xgifb_reg_set(P3c4, 0x1B, 0x00); XGINew_DDR1x_MRS_XG20() 278 unsigned long P3d4 = Port, P3c4 = Port - 0x10; XGINew_DDR1x_DefaultRegister() local 295 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo); XGINew_DDR1x_DefaultRegister() 347 XGINew_DDR1x_MRS_340(P3c4, pVBInfo); XGINew_DDR1x_DefaultRegister() 355 unsigned long P3d4 = Port, P3c4 = Port - 0x10; XGINew_DDR2_DefaultRegister() local 383 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo); XGINew_DDR2_DefaultRegister() 385 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo); XGINew_DDR2_DefaultRegister() 408 unsigned long P3d4 = Port, P3c4 = Port - 0x10; XGINew_SetDRAMDefaultRegister340() local 483 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */ XGINew_SetDRAMDefaultRegister340() 485 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */ XGINew_SetDRAMDefaultRegister340() 488 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */ XGINew_SetDRAMDefaultRegister340() 490 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */ XGINew_SetDRAMDefaultRegister340() 499 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */ XGINew_SetDRAMDefaultRegister340() 512 data = xgifb_reg_get(pVBInfo->P3c4, 0x13); XGINew_SetDRAMSize20Reg() 532 xgifb_reg_set(pVBInfo->P3c4, XGINew_SetDRAMSize20Reg() 534 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | XGINew_SetDRAMSize20Reg() 577 data = xgifb_reg_get(pVBInfo->P3c4, 0x39); XGINew_CheckFrequence() 603 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); XGINew_CheckChannel() 604 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52); XGINew_CheckChannel() 613 xgifb_reg_set(pVBInfo->P3c4, XGINew_CheckChannel() 616 xgifb_reg_set(pVBInfo->P3c4, XGINew_CheckChannel() 632 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); XGINew_CheckChannel() 633 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); XGINew_CheckChannel() 638 xgifb_reg_set(pVBInfo->P3c4, XGINew_CheckChannel() 649 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); XGINew_CheckChannel() 651 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); XGINew_CheckChannel() 660 xgifb_reg_set(pVBInfo->P3c4, XGINew_CheckChannel() 664 xgifb_reg_set(pVBInfo->P3c4, XGINew_CheckChannel() 680 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); XGINew_CheckChannel() 682 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30); XGINew_CheckChannel() 689 xgifb_reg_set(pVBInfo->P3c4, XGINew_CheckChannel() 700 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/ XGINew_CheckChannel() 713 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); XGINew_CheckChannel() 714 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44); XGINew_CheckChannel() 719 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); XGINew_CheckChannel() 720 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34); XGINew_CheckChannel() 725 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); XGINew_CheckChannel() 726 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40); XGINew_CheckChannel() 730 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); XGINew_CheckChannel() 731 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30); XGINew_CheckChannel() 735 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); XGINew_CheckChannel() 736 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52); XGINew_CheckChannel() 740 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); XGINew_CheckChannel() 741 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42); XGINew_CheckChannel() 751 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); XGINew_CheckChannel() 752 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C); XGINew_CheckChannel() 758 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48); XGINew_CheckChannel() 763 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); XGINew_CheckChannel() 764 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C); XGINew_CheckChannel() 770 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38); XGINew_CheckChannel() 775 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); XGINew_CheckChannel() 776 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A); XGINew_CheckChannel() 780 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); XGINew_CheckChannel() 781 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A); XGINew_CheckChannel() 794 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */ XGINew_DDRSizing340() 795 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */ XGINew_DDRSizing340() 810 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]); XGINew_DDRSizing340() 839 data = xgifb_reg_get(pVBInfo->P3c4, 0x21); XGINew_SetDRAMSize_340() 841 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); XGINew_SetDRAMSize_340() 845 data = xgifb_reg_get(pVBInfo->P3c4, 0x21); XGINew_SetDRAMSize_340() 847 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); XGINew_SetDRAMSize_340() 1206 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86); XGIInitNew() 1218 xgifb_reg_set(pVBInfo->P3c4, i, 0); XGIInitNew() 1221 xgifb_reg_set(pVBInfo->P3c4, i, 0); XGIInitNew() 1224 xgifb_reg_set(pVBInfo->P3c4, i, 0); XGIInitNew() 1228 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0); XGIInitNew() 1237 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07); XGIInitNew() 1239 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40); XGIInitNew() 1240 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41); XGIInitNew() 1242 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F); XGIInitNew() 1243 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F); XGIInitNew() 1245 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0); XGIInitNew() 1247 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70); XGIInitNew() 1249 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36); XGIInitNew() 1279 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23); XGIInitNew() 1280 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24); XGIInitNew() 1281 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0); XGIInitNew() 1298 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F); XGIInitNew() 1303 xgifb_reg_set(pVBInfo->P3c4, XGIInitNew() 1306 xgifb_reg_set(pVBInfo->P3c4, XGIInitNew() 1310 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31); XGIInitNew() 1311 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32); XGIInitNew() 1313 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33); XGIInitNew() 1358 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa); XGIInitNew() 1359 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3); XGIInitNew() 127 XGINew_DDRII_Bootup_XG27( struct xgi_hw_device_info *HwDeviceExtension, unsigned long P3c4, struct vb_device_info *pVBInfo) XGINew_DDRII_Bootup_XG27() argument 201 XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension, unsigned long P3c4, struct vb_device_info *pVBInfo) XGINew_DDR2_MRS_XG20() argument
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