Searched refs:MMP2_CLK_SDH1 (Results 1 - 7 of 7) sorted by relevance
| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/ |
| H A D | marvell,mmp2.h | 54 #define MMP2_CLK_SDH1 102 macro
|
| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| H A D | marvell,mmp2.h | 54 #define MMP2_CLK_SDH1 102 macro
|
| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| H A D | marvell,mmp2.h | 54 #define MMP2_CLK_SDH1 102 macro
|
| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/ |
| H A D | marvell,mmp2.h | 54 #define MMP2_CLK_SDH1 102 macro
|
| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/ |
| H A D | marvell,mmp2.h | 54 #define MMP2_CLK_SDH1 102 macro
|
| /linux-4.1.27/include/dt-bindings/clock/ |
| H A D | marvell,mmp2.h | 54 #define MMP2_CLK_SDH1 102 macro
|
| /linux-4.1.27/drivers/clk/mmp/ |
| H A D | clk-of-mmp2.c | 225 {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
226 {MMP2_CLK_SDH1, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
227 {MMP2_CLK_SDH1, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
|
Completed in 68 milliseconds