Searched refs:MIF_SCLK_LPDDR3PHY_WRAP_U0 (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dexynos5260-clk.h205 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dexynos5260-clk.h205 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dexynos5260-clk.h205 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dexynos5260-clk.h205 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dexynos5260-clk.h205 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dexynos5260-clk.h205 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 macro
/linux-4.1.27/drivers/clk/samsung/
H A Dclk-exynos5260.c1143 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",

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