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Searched refs:MFC_STATE1_MASTER_RUN_CONTROL_MASK (Results 1 – 6 of 6) sorted by relevance

/linux-4.1.27/arch/powerpc/platforms/cell/spufs/
Dhw_ops.c245 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_start()
256 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_stop()
Dbacking_ops.c314 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_start()
325 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_stop()
Dswitch.c510 spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK | in setup_mfc_sr1()
1057 MFC_STATE1_MASTER_RUN_CONTROL_MASK); in clear_spu_status()
1069 MFC_STATE1_MASTER_RUN_CONTROL_MASK); in clear_spu_status()
1898 spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK); in force_spu_isolate_exit()
2164 MFC_STATE1_MASTER_RUN_CONTROL_MASK | in init_priv1()
/linux-4.1.27/arch/powerpc/include/asm/
Dspu.h496 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull macro
/linux-4.1.27/arch/powerpc/platforms/cell/
Dspu_base.c718 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in crash_kexec_stop_spus()
/linux-4.1.27/arch/powerpc/xmon/
Dxmon.c3075 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in stop_spus()