Searched refs:MCLK (Results 1 - 170 of 170) sorted by relevance

/linux-4.1.27/sound/soc/codecs/
H A Dwm9713.h27 /* MCLK clock mulitipliers */
33 /* MCLK clock MUX */
H A Dda9055.c255 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
256 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
257 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
258 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
259 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
260 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
261 {19200000, 2822400, 0x1A, 0x1C, 0x12, 1}, /* MCLK=19.2Mhz */
262 {19680000, 2822400, 0x0B, 0x6D, 0x12, 1}, /* MCLK=19.68Mhz */
263 {19800000, 2822400, 0x07, 0xDD, 0x12, 1}, /* MCLK=19.8Mhz */
265 {11289600, 3072000, 0x1A, 0x8E, 0x22, 1}, /* MCLK=11.2896Mhz */
266 {12000000, 3072000, 0x18, 0x93, 0x20, 1}, /* MCLK=12Mhz */
267 {12288000, 3072000, 0x00, 0x00, 0x20, 1}, /* MCLK=12.288Mhz */
268 {13000000, 3072000, 0x07, 0xEA, 0x1E, 1}, /* MCLK=13Mhz */
269 {13500000, 3072000, 0x04, 0x11, 0x1D, 1}, /* MCLK=13.5Mhz */
270 {14400000, 3072000, 0x09, 0xD0, 0x1B, 1}, /* MCLK=14.4Mhz */
271 {19200000, 3072000, 0x0F, 0x5C, 0x14, 1}, /* MCLK=19.2Mhz */
272 {19680000, 3072000, 0x1F, 0x60, 0x13, 1}, /* MCLK=19.68Mhz */
273 {19800000, 3072000, 0x1B, 0x80, 0x13, 1}, /* MCLK=19.8Mhz */
275 {11289600, 2822400, 0x0D, 0x47, 0x21, 0}, /* MCLK=11.2896Mhz */
276 {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0}, /* MCLK=12Mhz */
277 {12288000, 2822400, 0x16, 0x66, 0x1E, 0}, /* MCLK=12.288Mhz */
278 {13000000, 2822400, 0x00, 0x98, 0x1D, 0}, /* MCLK=13Mhz */
279 {13500000, 2822400, 0x1E, 0x33, 0x1B, 0}, /* MCLK=13.5Mhz */
280 {14400000, 2822400, 0x06, 0x50, 0x1A, 0}, /* MCLK=14.4Mhz */
281 {19200000, 2822400, 0x14, 0xBC, 0x13, 0}, /* MCLK=19.2Mhz */
282 {19680000, 2822400, 0x05, 0x66, 0x13, 0}, /* MCLK=19.68Mhz */
283 {19800000, 2822400, 0x01, 0xAE, 0x13, 0}, /* MCLK=19.8Mhz */
1135 * When PLL is bypassed, chip assumes constant MCLK of da9055_hw_params()
1136 * 12.288MHz and uses sample rate value to divide this MCLK da9055_hw_params()
1264 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n", da9055_set_dai_sysclk()
1279 * @param fref : Input MCLK frequency
H A Dda7210.c228 { 12000000, 2822400, 0xE8, 0x6C, 0x2, 1}, /* MCLK=12Mhz */
229 { 13000000, 2822400, 0xDF, 0x28, 0xC, 1}, /* MCLK=13Mhz */
230 { 13500000, 2822400, 0xDB, 0x0A, 0xD, 1}, /* MCLK=13.5Mhz */
231 { 14400000, 2822400, 0xD4, 0x5A, 0x2, 1}, /* MCLK=14.4Mhz */
232 { 19200000, 2822400, 0xBB, 0x43, 0x9, 1}, /* MCLK=19.2Mhz */
233 { 19680000, 2822400, 0xB9, 0x6D, 0xA, 1}, /* MCLK=19.68Mhz */
234 { 19800000, 2822400, 0xB8, 0xFB, 0xB, 1}, /* MCLK=19.8Mhz */
236 { 12000000, 3072000, 0xF3, 0x12, 0x7, 1}, /* MCLK=12Mhz */
237 { 13000000, 3072000, 0xE8, 0xFD, 0x5, 1}, /* MCLK=13Mhz */
238 { 13500000, 3072000, 0xE4, 0x82, 0x3, 1}, /* MCLK=13.5Mhz */
239 { 14400000, 3072000, 0xDD, 0x3A, 0x0, 1}, /* MCLK=14.4Mhz */
240 { 19200000, 3072000, 0xC1, 0xEB, 0x8, 1}, /* MCLK=19.2Mhz */
241 { 19680000, 3072000, 0xBF, 0xEC, 0x0, 1}, /* MCLK=19.68Mhz */
242 { 19800000, 3072000, 0xBF, 0x70, 0x0, 1}, /* MCLK=19.8Mhz */
244 { 12000000, 2822400, 0xED, 0xBF, 0x5, 0}, /* MCLK=12Mhz */
245 { 13000000, 2822400, 0xE4, 0x13, 0x0, 0}, /* MCLK=13Mhz */
246 { 13500000, 2822400, 0xDF, 0xC6, 0x8, 0}, /* MCLK=13.5Mhz */
247 { 14400000, 2822400, 0xD8, 0xCA, 0x1, 0}, /* MCLK=14.4Mhz */
248 { 19200000, 2822400, 0xBE, 0x97, 0x9, 0}, /* MCLK=19.2Mhz */
249 { 19680000, 2822400, 0xBC, 0xAC, 0xD, 0}, /* MCLK=19.68Mhz */
250 { 19800000, 2822400, 0xBC, 0x35, 0xE, 0}, /* MCLK=19.8Mhz */
970 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n", da7210_set_dai_sysclk()
985 * @param fref : MCLK frequency, should be < 20MHz
H A Dcs4270.c19 * cs4270_set_dai_sysclk() with the value of MCLK.
133 unsigned int mclk; /* Input frequency of the MCLK pin */
160 * @ratio: the ratio of MCLK to the sample rate
176 * @mclk is the corresponding bit pattern to be wirten to the MCLK bits of
210 /* The number of MCLK/LRCK ratios supported by the CS4270 */
231 * @freq: the MCLK input frequency
234 * This function is used to tell the codec driver what the input MCLK
237 * The value of MCLK is used to determine which sample rates are supported
238 * by the CS4270. The ratio of MCLK / Fs must be equal to one of nine
337 /* Figure out which MCLK/LRCK ratio to use */ cs4270_hw_params()
340 ratio = cs4270->mclk / rate; /* MCLK/LRCK ratio */ cs4270_hw_params()
H A Dwm8510.h86 /* MCLK clock dividers */
H A Dwm8940.h77 /* MCLK clock dividers */
H A Dwm8974.h76 /* MCLK clock dividers */
H A Dwm8978.c442 /* MCLK dividers */
487 /* Cannot set up MCLK divider now, do later */ wm8978_configure_pll()
522 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK wm8978_configure_pll()
578 * We know the MCLK frequency, the user has requested wm8978_set_dai_clkdiv()
588 * find an exact MCLK divider configuration - it will wm8978_set_dai_clkdiv()
608 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
622 /* Even if MCLK is used for system clock, might have to drive OPCLK */ wm8978_set_dai_sysclk()
633 /* Clock CODEC directly from MCLK */ wm8978_set_dai_sysclk()
775 /* Sampling rate is known now, can configure the MCLK divider */ wm8978_hw_params()
792 /* Either MCLK is used directly, or OPCLK is used */ wm8978_hw_params()
820 dev_dbg(codec->dev, "%s: width %d, rate %u, MCLK divisor #%d\n", __func__, wm8978_hw_params()
823 /* MCLK divisor mask = 0xe0 */ wm8978_hw_params()
831 /* Run CODEC from PLL instead of MCLK */ wm8978_hw_params()
835 /* Clock CODEC directly from MCLK */ wm8978_hw_params()
H A Dwm8961.c517 dev_err(codec->dev, "MCLK has not been specified\n"); wm8961_hw_params()
605 dev_err(codec->dev, "MCLK must be <33MHz\n"); wm8961_set_sysclk()
610 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq); wm8961_set_sysclk()
614 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq); wm8961_set_sysclk()
H A Dwm8523.c123 * MCLK supplied to the CODEC - enforce this. wm8523_startup()
127 "No MCLK configured, call set_sysclk() on init\n"); wm8523_startup()
157 dev_err(codec->dev, "MCLK/fs ratio %d unsupported\n", wm8523_hw_params()
H A Dwm8776.c287 /* Only need to set MCLK/LRCLK ratio if we're master */ wm8776_hw_params()
297 "Unable to configure MCLK ratio %d/%d\n", wm8776_hw_params()
302 dev_dbg(codec->dev, "MCLK is %dfs\n", mclk_ratios[i]); wm8776_hw_params()
H A Dmax9850.c91 SND_SOC_DAPM_SUPPLY("MCLK", MAX9850_ENABLE, 6, 0, NULL, 0),
127 {"DAC", NULL, "MCLK"},
H A Dwm2000.c153 dev_dbg(&i2c->dev, "Disabling MCLK divider\n"); wm2000_power_up()
157 dev_dbg(&i2c->dev, "Enabling MCLK divider\n"); wm2000_power_up()
567 dev_err(&i2c->dev, "Failed to enable MCLK: %d\n", ret); wm2000_anc_transition()
875 wm2000->mclk = devm_clk_get(&i2c->dev, "MCLK"); wm2000_i2c_probe()
878 dev_err(&i2c->dev, "Failed to get MCLK: %d\n", ret); wm2000_i2c_probe()
H A Drt286.c630 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
707 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
708 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
709 {"Front", NULL, "MCLK MODE", is_mclk_mode},
710 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
928 dev_err(codec->dev, "Should not use MCLK\n"); rt286_set_dai_sysclk()
936 dev_err(codec->dev, "Should not use MCLK\n"); rt286_set_dai_sysclk()
H A Dcs4271.c196 * @freq is the desired MCLK rate
197 * MCLK rate should (c) be the sample rate, multiplied by one of the
306 unsigned short ratio; /* MCLK / sample rate */
H A Dwm8741.c205 * MCLK supplied to the CODEC - enforce this. wm8741_startup()
209 "No MCLK configured, call set_sysclk() on init\n"); wm8741_startup()
238 dev_err(codec->dev, "MCLK/fs ratio %d unsupported\n", wm8741_hw_params()
H A Dwm8770.c452 /* Only need to set MCLK/LRCLK ratio if we're master */ wm8770_hw_params()
462 "Unable to configure MCLK ratio %d/%d\n", wm8770_hw_params()
467 dev_dbg(codec->dev, "MCLK is %dfs\n", mclk_ratios[i]); wm8770_hw_params()
H A Dak5386.c108 * All external clocks (MCLK, SCLK and LRCK) must be present unless ak5386_hw_params()
H A Dwm8731.c683 dev_warn(&spi->dev, "Assuming static MCLK\n"); wm8731_spi_probe()
685 dev_err(&spi->dev, "Failed to get MCLK: %d\n", wm8731_spi_probe()
747 dev_warn(&i2c->dev, "Assuming static MCLK\n"); wm8731_i2c_probe()
749 dev_err(&i2c->dev, "Failed to get MCLK: %d\n", wm8731_i2c_probe()
H A Dcs42l73.c892 /* MCLK, Sample Rate, xMMCC[5:0] */
988 /* MCLKX -> MCLK */ cs42l73_set_mclk()
996 dev_dbg(codec->dev, "MCLK%u %u <-> internal MCLK %u\n", cs42l73_set_mclk()
1027 dev_err(codec->dev, "Unable to set MCLK for dai %s\n", cs42l73_set_sysclk()
1160 /* MCLK -> srate */ cs42l73_pcm_hw_params()
1168 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n", cs42l73_pcm_hw_params()
1175 /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */ cs42l73_pcm_hw_params()
H A Dda7213.c1236 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n", da7213_set_dai_sysclk()
1264 /* Workout input divider based on MCLK rate */ da7213_set_dai_pll()
1272 /* 5 - 54MHz MCLK */ da7213_set_dai_pll()
1310 /* Enable MCLK squarer if required */ da7213_set_dai_pll()
1511 /* Set MCLK squaring */ da7213_probe()
H A Dsta32x.c542 /* MCLK interpolation ratio per fs */
556 /* MCLK to fs clock ratios */
564 * sta32x_set_dai_sysclk - configure MCLK
567 * @freq: the MCLK input frequency
570 * The value of MCLK is used to determine which sample rates are supported
H A Dsta350.c578 /* MCLK interpolation ratio per fs */
592 /* MCLK to fs clock ratios */
600 * sta350_set_dai_sysclk - configure MCLK
603 * @freq: the MCLK input frequency
606 * The value of MCLK is used to determine which sample rates are supported
H A Dwm8988.c652 * MCLK supplied to the CODEC - enforce this. wm8988_pcm_startup()
656 "No MCLK configured, call set_sysclk() on init\n"); wm8988_pcm_startup()
684 "Unable to configure sample rate %dHz with %dHz MCLK\n", wm8988_pcm_hw_params()
H A Dcs42l51.c363 /* Figure out which MCLK/LRCK ratio to use */ cs42l51_hw_params()
365 ratio = cs42l51->mclk / rate; /* MCLK/LRCK ratio */ cs42l51_hw_params()
H A Dmax98925.c472 /* use MCLK for Left channel, right channel always BCLK */ max98925_dai_set_sysclk()
478 /* configure dai clock source to BCLK instead of MCLK */ max98925_dai_set_sysclk()
H A Dwm8510.c323 /* Clock CODEC directly from MCLK */ wm8510_set_dai_pll()
342 /* Run CODEC from PLL instead of MCLK */ wm8510_set_dai_pll()
H A Dwm8737.c352 dev_err(codec->dev, "%dHz MCLK can't support %dHz\n", wm8737_hw_params()
398 dev_err(codec->dev, "MCLK rate %dHz not supported\n", freq); wm8737_set_dai_sysclk()
H A Dwm8974.c327 /* Clock CODEC directly from MCLK */ wm8974_set_dai_pll()
346 /* Run CODEC from PLL instead of MCLK */ wm8974_set_dai_pll()
H A Dcs42l73.h186 /* CS42L73 MCLK derived from MCLK1 or MCLK2 */
H A Dtlv320aic26.c164 /* MCLK needs to fall between 2MHz and 50 MHz */ aic26_set_sysclk()
H A Dwm8940.c589 /* Clock CODEC directly from MCLK */ wm8940_set_dai_pll()
612 /* Run CODEC from PLL instead of MCLK */ wm8940_set_dai_pll()
H A Dwm8955.c277 /* If we can't generate the right clock from MCLK then wm8955_configure_clocking()
289 "Unable to generate %dHz from %dHz MCLK\n", wm8955_configure_clocking()
H A Dwm9081.h21 #define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
22 #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */
H A Dalc5632.c662 /* FOUT = MCLK*(N+2)/((M+2)*(K+2))
713 /* PLL source from MCLK */ alc5632_set_dai_pll()
748 /* choose MCLK/BCLK/VBCLK */ alc5632_set_dai_pll()
H A Dwm9081.c665 * directly from MCLK and only use the FLL if this is configure_clock()
743 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate); clk_sys_event()
746 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n", clk_sys_event()
H A Dcs35l32.c516 /* Clear MCLK Error Bit since we don't have the clock yet */ cs35l32_i2c_probe()
H A Dssm2518.c664 * the bitclock signal needs to be connected to the MCLK pin and ssm2518_set_sysclk()
H A Dtas5086.c382 /* MCLK / Fs ratio */ tas5086_hw_params()
386 dev_err(codec->dev, "Inavlid MCLK / Fs ratio\n"); tas5086_hw_params()
H A Dwm8960.c636 "Failed to enable MCLK: %d\n", wm8960_set_bias_level_out3()
749 "Failed to enable MCLK: %d\n", wm8960_set_bias_level_capless()
H A Dwm8983.c771 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n", wm8983_hw_params()
776 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio); wm8983_hw_params()
H A Dwm8985.c750 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n", wm8985_hw_params()
755 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio); wm8985_hw_params()
H A Des8328.c469 /* find master mode MCLK to sampling frequency ratio */ es8328_hw_params()
H A Dwm8903.c1500 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", wm8903_hw_params()
1503 /* We may not have an MCLK which allows us to generate exactly wm8903_hw_params()
H A Dwm8904.c332 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); wm8904_configure_clocking()
2141 dev_err(&i2c->dev, "Failed to get MCLK\n"); wm8904_i2c_probe()
H A Dalc5623.c555 /* PLL source from MCLK */ alc5623_set_dai_pll()
H A Dtlv320aic31xx.c924 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ aic31xx_set_dai_sysclk()
H A Dwm8350.c779 /* MCLK direction */ wm8350_set_dai_sysclk()
H A Dwm8900.c16 * - FLL source configuration, currently only MCLK is supported.
H A Dwm8993.c587 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate); configure_clock()
H A Dwm8753.c1173 printk(KERN_ERR "wm8753 invalid MCLK or rate\n"); wm8753_i2s_hw_params()
H A Dtlv320aic3x.c1208 /* set clock on MCLK or GPIO2 or BCLK */ aic3x_set_dai_sysclk()
H A Drt5645.c625 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
H A Drt5670.c782 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5670 can
H A Dwm8962.c3796 dev_err(dev, "Failed to enable MCLK: %d\n", ret); wm8962_runtime_resume()
H A Drt5677.c1046 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
/linux-4.1.27/include/sound/
H A Dda7213.h48 /* MCLK squaring config */
H A Dcs4271.h25 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET
/linux-4.1.27/sound/soc/samsung/
H A Dsmdk_wm8580pcm.c40 * If MCLK clock directly gets from XTAL, we don't have to use PLL
41 * to make MCLK, but if XTAL clock source connects with other codec
42 * pin (like XTI), we should have to set codec's PLL to make MCLK.
145 * 2.0484Mhz, directly with MCLK both Codec and SoC.
H A Dsnow.c42 /* Set the MCLK rate for the codec */ snow_late_probe()
H A Dh1940_uda1380.c103 /* set MCLK division for sample rate */ h1940_hw_params()
H A Drx1950_uda1380.c191 /* set MCLK division for sample rate */ rx1950_hw_params()
H A Dsmdk_wm8580.c79 /* Set WM8580 to drive MCLK from its PLLA */ smdk_hw_params()
H A Dbells.c207 dev_err(wm9081_dai->dev, "Failed to set MCLK: %d\n", ret); bells_late_probe()
H A Dneo1973_wm8753.c79 /* set MCLK division for sample rate */ neo1973_hifi_hw_params()
/linux-4.1.27/arch/arm/mach-ks8695/include/mach/
H A Dhardware.h20 * Clocks are derived from MCLK, which is 25Mhz
/linux-4.1.27/arch/unicore32/kernel/
H A Ddebug-macro.S40 /* Uartclk = MCLK/ 2, The MCLK on my board is 3686400 * 40 */
/linux-4.1.27/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c28 /* helpers to keep the MCLK intermediates "somewhere" in our table */
64 /* intermediates for the mux+gate+div+mux MCLK generation */
465 /* MCLK helpers {{{ */
468 * helper code for the MCLK subtree setup
594 /* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */ mpc512x_clk_setup_mclk()
598 u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */ mpc512x_clk_setup_mclk()
634 * enforced a specific MCLK divider while the clock was gated mpc512x_clk_setup_mclk()
638 * "MCLK <= IPS" constraint, the fixed divider value of 1 mpc512x_clk_setup_mclk()
639 * results in a divider of 2 and thus MCLK = SYS/2 which equals mpc512x_clk_setup_mclk()
645 * - MCLK 0 from SYS mpc512x_clk_setup_mclk()
646 * - MCLK DIV such to not exceed the IPS clock mpc512x_clk_setup_mclk()
647 * - MCLK 0 enabled mpc512x_clk_setup_mclk()
648 * - MCLK 1 from MCLK DIV mpc512x_clk_setup_mclk()
657 * create the 'struct clk' items of the MCLK's clock subtree mpc512x_clk_setup_mclk()
663 * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK mpc512x_clk_setup_mclk()
702 /* }}} MCLK helpers */
820 /* for PSCs there is a "registers" gate and a bitrate MCLK subtree */ mpc512x_clk_setup_clock_tree()
868 /* there is only one SPDIF component, which shares MCLK support code */ mpc512x_clk_setup_clock_tree()
/linux-4.1.27/sound/soc/omap/
H A Dosk5912.c149 * Configure 12 MHz output on MCLK. osk_soc_init()
154 printk(KERN_ERR "Cannot set MCLK for AIC23 CODEC\n"); osk_soc_init()
160 printk(KERN_INFO "MCLK = %d [%d]\n", osk_soc_init()
H A Domap-abe-twl6040.c40 int mclk_freq; /* MCLK frequency speed for twl6040 */
301 dev_err(&pdev->dev, "MCLK frequency not provided\n"); omap_abe_probe()
309 dev_err(&pdev->dev, "MCLK frequency missing\n"); omap_abe_probe()
/linux-4.1.27/sound/soc/mxs/
H A Dmxs-saif.c87 * Set SAIF clock and MCLK
122 * If MCLK is used, the SAIF clk ratio need to match mclk ratio. mxs_saif_set_clk()
126 * If MCLK is not used, we just set saif clk to 512*fs. mxs_saif_set_clk()
138 /* SAIF MCLK should be either 32x or 48x */ mxs_saif_set_clk()
160 * Program the over-sample rate for MCLK output mxs_saif_set_clk()
162 * The available MCLK range is 32x, 48x... 512x. The rate mxs_saif_set_clk()
203 * Put and disable MCLK.
221 /* disable MCLK output */ mxs_saif_put_mclk()
233 * Get MCLK and set clock rate, then enable it
235 * This interface is used for codecs who are using MCLK provided
278 /* enable MCLK output */ mxs_saif_get_mclk()
H A Dmxs-sgtl5000.c52 /* Set SGTL5000's SYSCLK (provided by SAIF MCLK) */ mxs_sgtl5000_hw_params()
60 /* The SAIF MCLK should be the same as SGTL5000_SYSCLK */ mxs_sgtl5000_hw_params()
/linux-4.1.27/arch/arm/mach-ebsa110/
H A Dcore.c140 * This is the rate at which your MCLK signal toggles (in Hz)
144 #define MCLK 47894000 macro
149 #define CLKBY7 (MCLK / 7)
286 * will stop our MCLK signal (which provides the clock for the glue
/linux-4.1.27/sound/soc/intel/boards/
H A Dcht_bsw_rt5672.c29 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
77 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ platform_clock_control()
94 * PLL will be off when idle and MCLK will also be off by ACPI platform_clock_control()
151 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ cht_aif1_hw_params()
H A Dcht_bsw_rt5645.c74 * be off when idle and MCLK will also be off by ACPI when codec is platform_clock_control()
132 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ cht_aif1_hw_params()
/linux-4.1.27/arch/arm/mach-sa1100/
H A Dpleb.c132 GPCR = GPIO_ETH0_EN; /* clear MCLK (enable smc) */ pleb_map_io()
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Dit8152.h52 IT8152_LD_IRQ(7) MCLK ready
/linux-4.1.27/sound/pci/oxygen/
H A Dcs4245.h56 /* MCLK Frequency */
H A Doxygen_regs.h141 #define OXYGEN_I2S_MCLK_MASK 0x0030 /* MCLK/LRCK */
H A Dxonar_pcm179x.c111 * ADC1 MCLK -> REF_CLK of CS2000 (ST only)
155 * ADC1 MCLK -> REF_CLK of CS2000
H A Doxygen.c360 msleep(1); /* wait for the new MCLK to become stable */ set_ak4396_params()
/linux-4.1.27/sound/soc/atmel/
H A Dsam9g20_wm8731.c182 * Codec MCLK is supplied by PCK0 - set it up. at91sam9g20ek_audio_probe()
186 printk(KERN_ERR "ASoC: Failed to get MCLK\n"); at91sam9g20ek_audio_probe()
200 printk(KERN_ERR "ASoC: Failed to set MCLK parent\n"); at91sam9g20ek_audio_probe()
/linux-4.1.27/sound/soc/pxa/
H A Dzylonite.c29 * There is a physical switch SW15 on the board which changes the MCLK
35 MODULE_PARM_DESC(clk_pout, "Use CLK_POUT as WM9713 MCLK (SW15 on board).");
191 dev_dbg(card->dev, "MCLK enabled at %luHz\n", zylonite_probe()
/linux-4.1.27/drivers/staging/sm750fb/
H A Dddk750_chip.c175 * This function set up the master clock (MCLK).
204 ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3); setMasterClock()
207 ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4); setMasterClock()
210 ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6); setMasterClock()
213 ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8); setMasterClock()
/linux-4.1.27/drivers/net/can/mscan/
H A Dmpc5xxx_can.c143 * MSCAN related MCLK is the input to the MSCAN component mpc512x_can_get_clock()
195 /* select IPS or MCLK as the MSCAN input (returned to the caller), mpc512x_can_get_clock()
196 * setup the MCLK mux source and rate if applicable, apply the mpc512x_can_get_clock()
231 dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n", mpc512x_can_get_clock()
/linux-4.1.27/drivers/spi/
H A Dspi-mpc52xx-psc.c31 #define MCLK 20000000 /* PSC port MClk in hz */ macro
109 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; mpc52xx_psc_spi_activate_cs()
111 ccr |= (MCLK / 1000000 - 1) & 0xFF; mpc52xx_psc_spi_activate_cs()
321 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; mpc52xx_psc_spi_port_config()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dbsbe1.h30 0x02, 0x30, /* MCLK = 88 MHz */
H A Dstb0899_drv.c1539 /* Set IterScale =f(MCLK,SYMB) */ stb0899_search()
H A Ddrxk_hard.c1440 /* Suppress MCLK during absence of data */ mpegts_stop()
2055 /* Rational DTO for MCLK source (static MCLK rate), mpegts_dto_setup()
/linux-4.1.27/sound/soc/cirrus/
H A Dedb93xx.c42 * According to CS4271 datasheet we use MCLK/LRCK=256 for edb93xx_hw_params()
H A Dep93xx-i2s.c277 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. ep93xx_i2s_hw_params()
/linux-4.1.27/sound/soc/fsl/
H A Dwm1133-ev1.c103 /* codec FLL input is 14.75 MHz from MCLK */ wm1133_ev1_hw_params()
118 /* set MCLK as the codec system clock for DAC and ADC */ wm1133_ev1_hw_params()
H A Dfsl-asoc-card.c36 * @mclk_freq: Clock rate of MCLK
37 * @mclk_id: MCLK (or main clock) id for set_sysclk()
446 /* Get the MCLK rate only, and leave it controlled by CODEC drivers */ fsl_asoc_card_probe()
H A Dmpc8610_hpcd.c119 * Tell the codec driver what the MCLK frequency is, and whether it's mpc8610_hpcd_startup()
H A Dp1022_ds.c142 * Tell the codec driver what the MCLK frequency is, and whether it's p1022_ds_startup()
H A Dfsl_esai.c200 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
/linux-4.1.27/drivers/video/fbdev/aty/
H A Dmach64_ct.c60 * x depends on the type of clock; usually it is 2, but for the MCLK it can also
68 * MCLK The clock rate of the chip
78 * - MCLK and XCLK use the same FB_DIV
89 * - Clock the chip instead of MCLK
95 * It can be quite hard to calculate XCLK and MCLK if they don't run at the
H A Dradeon_pm.c1540 /* Select source for MCLK */ radeon_pm_start_mclk_sclk()
1802 /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */ radeon_reinitialize_M10()
1888 /* Now we actually start MCLK and SCLK */ radeon_reinitialize_M10()
2042 /* Force MCLK to be PCI sourced and forced ON */ radeon_reinitialize_M9P()
2120 /* Now we actually start MCLK and SCLK */ radeon_reinitialize_M9P()
H A Dradeon_base.c423 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
445 val = of_get_property(dp, "ATY,MCLK", NULL); radeon_read_xtal_OF()
700 * Some methods fail to retrieve SCLK and MCLK values, we apply default radeon_get_pllinfo()
H A Daty128fb.c293 u16 MCLK; member in struct:__anon10492
H A Datyfb_base.c44 - guess PLL and MCLK based on the original PLL register values initialized
2572 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n", aty_init()
/linux-4.1.27/drivers/video/fbdev/matrox/
H A Dmatroxfb_Ti3026.c204 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
485 /* stop MCLK */ ti3026_setMCLK()
517 /* output MCLK to MCLK pin */ ti3026_setMCLK()
H A Dmatroxfb_DAC1064.c108 /* read MCLK and give up... */ DBG()
134 /* !!! you must not access device if MCLK is not running !!!
596 /* maybe cmdline MCLK= ?, doc says gclk=44MHz, mclk=66MHz... it was 55/83 with old values */ MGA1064_ramdac_init()
1008 /* either leave MCLK as is... or they were set in preinit */
/linux-4.1.27/drivers/video/fbdev/
H A Dasiliantfb.c434 {0xcc, 200 }, /* MCLK ratio M */
435 {0xcd, 18 }, /* MCLK ratio N */
436 {0xce, 0x90}, /* MCLK divisor = 2 */
H A Dcirrusfb.c13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
448 /* Check if the MCLK is not a better clock source */ cirrusfb_check_mclk()
454 /* Read MCLK value */ cirrusfb_check_mclk()
456 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk); cirrusfb_check_mclk()
458 /* Determine if we should use MCLK instead of VCLK, and if so, what we cirrusfb_check_mclk()
463 dev_dbg(info->device, "Using VCLK = MCLK\n"); cirrusfb_check_mclk()
466 dev_dbg(info->device, "Using VCLK = MCLK/2\n"); cirrusfb_check_mclk()
642 (div == 2) ? "MCLK/2" : "MCLK"); cirrusfb_set_mclk_as_source()
2282 /* MCLK select etc. */ cirrusfb_zorro_register()
H A Dcyber2000fb.c1766 * Use MCLK from BIOS. FIXME: what about hotplug? cyberpro_pci_probe()
1773 * MCLK on the NetWinder and the Shark is fixed at 75MHz cyberpro_pci_probe()
H A Ds3fb.c1258 /* Find MCLK frequency */ s3_pci_probe()
1354 fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n", s3_pci_probe()
H A Di740fb.c638 /* Set the MCLK freq */ i740fb_decode_var()
H A Dimsttfb.c214 TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
/linux-4.1.27/sound/soc/xtensa/
H A Dxtfpga-i2s.c303 /* ratio field of the config register controls MCLK->I2S clock xtfpga_i2s_hw_params()
304 * derivation: I2S clock = MCLK / (2 * (ratio + 2)). xtfpga_i2s_hw_params()
306 * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo xtfpga_i2s_hw_params()
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dsmu7.h42 #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM
H A Drv740_dpm.c116 DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n"); rv740_get_dll_speed()
H A Dradeon_clocks.c96 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
157 val = of_get_property(dp, "ATY,MCLK", NULL); radeon_read_clocks_OF()
/linux-4.1.27/arch/arm/mm/
H A Dproc-sa110.S97 ldr r1, [r1, #0] @ force switch to MCLK
H A Dproc-sa1100.S112 ldr r1, [r1, #0] @ force switch to MCLK
/linux-4.1.27/sound/soc/blackfin/
H A Dbf5xx-ad73311.c82 /* DMCLK = MCLK = 16.384 MHz snd_ad73311_configure()
/linux-4.1.27/include/linux/mfd/arizona/
H A Dpdata.h87 /** If a direct 32kHz clock is provided on an MCLK specify it here */
/linux-4.1.27/drivers/pinctrl/sunxi/
H A Dpinctrl-sun7i-a20.c86 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
162 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
170 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
171 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
479 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
H A Dpinctrl-sun6i-a31s.c199 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
482 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
665 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
H A Dpinctrl-sun6i-a31.c226 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
559 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
649 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
749 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
H A Dpinctrl-sun9i-a80.c147 SUNXI_FUNCTION(0x3, "mcsi"), /* MCLK */
404 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
H A Dpinctrl-sun5i-a13.c253 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
H A Dpinctrl-sun4i-a10.c146 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
147 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
449 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
H A Dpinctrl-sun8i-a23.c350 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
H A Dpinctrl-sun5i-a10s.c162 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
/linux-4.1.27/drivers/media/usb/tm6000/
H A Dtm6000-core.c623 u8 areg_f0 = 0x60; /* ADC MCLK = 250 Fs */ tm6000_set_audio_bitrate()
628 areg_f0 = 0x60; /* ADC MCLK = 250 Fs */ tm6000_set_audio_bitrate()
633 areg_f0 = 0x00; /* ADC MCLK = 375 Fs */ tm6000_set_audio_bitrate()
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
H A Dhdmi4_core.c566 * the MCLK, this is the first part of the MCLK initialization. hdmi_core_audio_config()
574 /* For devices using MCLK, this completes its initialization. */ hdmi_core_audio_config()
/linux-4.1.27/sound/pci/ice1712/
H A Dse.c208 se200pci_WM8766_write(ice, 0x0a, 0x080); /* MCLK=256fs */ se200pci_WM8766_init()
221 se200pci_WM8766_write(ice, 0x0a, 0x000); /* MCLK=128fs */ se200pci_WM8766_set_pro_rate()
223 se200pci_WM8766_write(ice, 0x0a, 0x080); /* MCLK=256fs */ se200pci_WM8766_set_pro_rate()
H A Dwm8766.c189 /* restore volume after MCLK stopped */ snd_wm8766_volume_restore()
H A Dwm8776.c463 /* restore volume after MCLK stopped */ snd_wm8776_volume_restore()
H A Dice1724.c647 val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */ stdclock_set_mclk()
649 val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */ stdclock_set_mclk()
/linux-4.1.27/drivers/mmc/host/
H A Dsdhci-msm.c263 /* Program the MCLK value to MCLK_FREQ bit field */ msm_cm_dll_set_freq()
509 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ sdhci_msm_probe()
H A Dmmci.c265 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. mmci_reg_delay()
828 * depends on the rate of MCLK. mmci_start_data()
/linux-4.1.27/drivers/video/fbdev/sis/
H A Dinit.c2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, SiS_DoCalcDelay() argument
2281 idx1 = longtemp % (MCLK * 16); SiS_DoCalcDelay()
2282 longtemp /= (MCLK * 16); SiS_DoCalcDelay()
2289 unsigned short colordepth, unsigned short MCLK) SiS_CalcDelay()
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; SiS_SetCRT1FIFO_300() local
2322 /* Get MCLK */ SiS_SetCRT1FIFO_300()
2324 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; SiS_SetCRT1FIFO_300()
2441 /* Get MCLK * 16 */ SiS_SetCRT1FIFO_630()
2288 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK, unsigned short colordepth, unsigned short MCLK) SiS_CalcDelay() argument
H A Dinit301.c5015 unsigned short VCLK = 0, MCLK, colorth = 0, data2 = 0; SiS_SetCRT2FIFO_300() local
5055 /* Get MCLK */ SiS_SetCRT2FIFO_300()
5062 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; SiS_SetCRT2FIFO_300()
5068 data2 = temp - ((colorth * VCLK) / MCLK); SiS_SetCRT2FIFO_300()
5148 temp = data % (MCLK << 4); SiS_SetCRT2FIFO_300()
5149 data = data / (MCLK << 4); SiS_SetCRT2FIFO_300()
H A Dsis_main.c4336 v1 = 0x68; v2 = 0x43; /* Assume 125Mhz MCLK */ sisfb_post_sis300()
/linux-4.1.27/include/video/
H A Dcirrus.h61 #define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */
/linux-4.1.27/arch/arm/mach-omap1/include/mach/
H A Dmux.h398 /* MCLK Settings */
/linux-4.1.27/drivers/video/fbdev/savage/
H A Dsavagefb_driver.c1088 if (par->MCLK <= 0) { savagefb_decode_var()
1092 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, savagefb_decode_var()
1094 /* reg->SR10 = 80; // MCLK == 286000 */ savagefb_decode_var()
1408 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates savagefb_set_par_int()
1946 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; savage_init_hw()
1947 printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n", savage_init_hw()
1948 par->MCLK); savage_init_hw()
H A Dsavagefb.h211 int MCLK, REFCLK, LCDclk; member in struct:savagefb_par
/linux-4.1.27/drivers/scsi/
H A Dnsp32.h308 # define CLOCK_2 BIT(0) /* MCLK/2 */
309 # define CLOCK_4 BIT(1) /* MCLK/4 */
/linux-4.1.27/drivers/staging/sm7xxfb/
H A Dsm7xxfb.c849 /* set MCLK = 14.31818 * (0x16 / 0x2) */ smtcfb_pci_probe()
985 /* set MCLK = 14.31818 * (0x16 / 0x2) */ smtcfb_pci_resume()
/linux-4.1.27/arch/arm/mach-omap1/
H A Dclock.c311 /* MCLK and BCLK divisor selection is not linear: calc_ext_dsor()
347 /* External clock (MCLK & BCLK) functions */ omap1_set_ext_clk_rate()
H A Dmux.c304 /* MCLK Settings */
/linux-4.1.27/sound/ppc/
H A Dsnd_ps3_reg.h348 MCLK Output Control
364 MCLK Output Control
/linux-4.1.27/sound/soc/intel/haswell/
H A Dsst-haswell-dsp.c272 /* disable MCLK(clkctl.smos = 0) */ hsw_set_dsp_D3()
347 /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ hsw_set_dsp_D0()
/linux-4.1.27/drivers/media/platform/marvell-ccic/
H A Dmcam-core.h116 int mclk_div; /* Clock Divider Value for MCLK */
/linux-4.1.27/arch/blackfin/mach-bf561/boards/
H A Dezkit.c650 * MCLK = 12.288MHz ezkit_init()
/linux-4.1.27/arch/m32r/include/asm/
H A Ds1d13806.h11 // Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
/linux-4.1.27/drivers/tty/serial/
H A Dmpc52xx_uart.c673 dev_err(port->dev, "Failed to get MCLK!\n"); mpc512x_psc_alloc_clock()
679 dev_err(port->dev, "Failed to enable MCLK!\n"); mpc512x_psc_alloc_clock()
750 dev_err(port->dev, "Failed to enable MCLK!\n"); mpc512x_psc_endis_clock()
/linux-4.1.27/include/linux/mfd/wm8350/
H A Daudio.h571 /* Sys (MCLK) clock dividers */
/linux-4.1.27/drivers/media/platform/soc_camera/
H A Dpxa_camera.c107 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
112 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
869 /* If we're not supplying MCLK, leave it at 0 */ mclk_get_divisor()
/linux-4.1.27/drivers/media/i2c/
H A Dsr030pc30.c601 * power and disabling MCLK. sr030pc30_s_power()
H A Dov9650.c1478 dev_err(&client->dev, "MCLK frequency not specified\n"); ov965x_probe()
H A Ds5k6aa.c1555 dev_err(&client->dev, "MCLK frequency not specified\n"); s5k6aa_probe()
H A Dadv7842.c2580 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ adv7842_core_init()
H A Dadv7604.c2421 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ adv76xx_core_init()
/linux-4.1.27/drivers/media/pci/cx25821/
H A Dcx25821-alsa.c235 /* enable output on the GPIO 0 for the MCLK ADC (Audio) */ _cx25821_start_audio_dma()
/linux-4.1.27/arch/arm/mach-pxa/
H A Draumfeld.c991 ret = gpio_request(GPIO_MCLK_RESET, "MCLK reset"); raumfeld_audio_init()
/linux-4.1.27/drivers/mfd/
H A Dsm501.c524 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK sm501_set_clock()
1268 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); sm501_init_regs()
/linux-4.1.27/drivers/gpu/drm/ast/
H A Dast_post.c1151 /* Wait MCLK2X lock to MCLK */ ddr3_init()
1520 /* Wait MCLK2X lock to MCLK */ ddr2_init()
/linux-4.1.27/drivers/media/i2c/soc_camera/
H A Dmt9t112.c643 /* MCLK: 16MHz mt9t112_init_setting()
/linux-4.1.27/drivers/clk/
H A Dclk-u300.c939 * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
/linux-4.1.27/sound/isa/cs423x/
H A Dcs4236_lib.c77 * D1: disable MCLK (all chips)
/linux-4.1.27/sound/pci/ca0106/
H A Dca0106.h605 #define SPI_RATE_BIT_128 (0<<6) /* MCLK = LRCLK * 128 */
/linux-4.1.27/sound/spi/
H A Dat73c213.c145 * The DAC master clock (MCLK) is programmable, and is either 256 snd_at73c213_set_bitrate()
/linux-4.1.27/sound/soc/
H A Dsoc-core.c2042 * Configures the DAI master (MCLK) or system (SYSCLK) clocking.
2065 * Configures the CODEC master (MCLK) or system (SYSCLK) clocking.
/linux-4.1.27/sound/soc/davinci/
H A Ddavinci-mcasp.c542 case 0: /* MCLK divider */ __davinci_mcasp_set_clkdiv()
/linux-4.1.27/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_driver.h1312 * MStart width [nr MCLK cycles] for serial MPEG output.
/linux-4.1.27/sound/pci/hda/
H A Dpatch_ca0132.c4186 /* MCLK uses MPIO1, set to enable. ca0132_init_dmic()

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