Searched refs:M0 (Results 1 – 7 of 7) sorted by relevance
| /linux-4.1.27/arch/xtensa/variants/dc232b/include/variant/ |
| D | tie-asm.h | 49 rsr \at1, M0 // MAC16 registers
92 wsr \at1, M0 // MAC16 registers
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| /linux-4.1.27/arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 9 -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
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| /linux-4.1.27/arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 9 -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
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| /linux-4.1.27/arch/xtensa/variants/dc233c/include/variant/ |
| D | tie-asm.h | 104 rsr \at1, M0 // MAC16 option
169 wsr \at1, M0 // MAC16 option
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| /linux-4.1.27/Documentation/frv/ |
| D | atomic-ops.txt | 88 " ld.p %M0,%1 \n" <-- (2)
99 " cst.p %1,%M0 ,cc3,#1 \n" <-- (4a)
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| /linux-4.1.27/Documentation/devicetree/bindings/arm/ |
| D | l2cc.txt | 46 addresses will go to the M0 port.
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| /linux-4.1.27/arch/arm/mach-omap2/ |
| D | mux34xx.c | 17 #define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ argument
19 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
26 #define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ argument
28 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
34 #define _OMAP3_BALLENTRY(M0, bb, bt) \ argument
36 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
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