Searched refs:LCDC (Results 1 - 59 of 59) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/tilcdc/
H A Dtilcdc_regs.h21 /* LCDC register definitions, based on da8xx-fb */
27 /* LCDC Status Register */
35 /* LCDC DMA Control Register */
47 /* LCDC Control Register */
51 /* LCDC Raster Control Register */
75 /* LCDC Raster Timing 2 Register */
85 /* LCDC Block */
H A Dtilcdc_drv.c18 /* LCDC DRM driver, based on da8xx-fb */
H A Dtilcdc_crtc.c319 * be sure to set Bit 10 for the V2 LCDC controller, tilcdc_crtc_mode_set()
/linux-4.1.27/arch/sh/include/asm/
H A Dsh7760fb.h2 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
18 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
95 /* Display types supported by the LCDC */
119 /* LCDC Pixclock sources */
127 /* LCDC pixclock input divider. Set to 1 at a minimum! */
181 /* set this member to 1 if you wish to use the LCDC's hardware
191 * more than the LCDC in terms of blanking (e.g. disable clock
/linux-4.1.27/arch/sh/boards/mach-se/7722/
H A Dsetup.c164 /* LCDC I/O */ se7722_setup()
172 /* LCDC */ se7722_setup()
177 __raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */ se7722_setup()
/linux-4.1.27/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh770x.c32 LCDC, PCC0, PCC1, enumerator in enum:__anon2620
64 INTC_VECT(LCDC, 0x9a0),
85 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
H A Dsetup-sh7720.c233 DMAC1, LCDC, SSL, enumerator in enum:__anon2622
253 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
277 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
/linux-4.1.27/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c29 USB, LCDC, enumerator in enum:__anon2625
58 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
92 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
113 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7366.c271 VEU2, LCDC, enumerator in enum:__anon2653
306 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
329 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
351 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
H A Dsetup-sh7343.c331 JPU, LCDC, enumerator in enum:__anon2652
370 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
394 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
416 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
H A Dsetup-sh7763.c246 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC, enumerator in enum:__anon2660
264 INTC_VECT(LCDC, 0x620),
316 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
332 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
H A Dsetup-sh7734.c334 LCDC, enumerator in enum:__anon2658
423 INTC_VECT(LCDC, 0xC40),
459 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
491 LCDC_M, /* LCDC, MIMLB */
517 { SCIF0, SCIF3, HSCIF, LCDC } },
H A Dsetup-sh7722.c546 IRDA, JPU, LCDC, enumerator in enum:__anon2654
582 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
607 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
629 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
H A Dsetup-sh7724.c906 LCDC, enumerator in enum:__anon2656
1010 INTC_VECT(LCDC, 0xF40),
1046 JPU, 0, 0, LCDC } },
1076 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
/linux-4.1.27/arch/sh/drivers/dma/
H A Ddmabrg.c18 * from USB-SRAM/Audio units to main memory (and also the LCDC; but that
19 * part is sensibly placed in the LCDC registers and requires no irqs)
/linux-4.1.27/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.h48 * struct sh_mobile_lcdc_chan - LCDC display channel
H A Dsh7760fb.c2 * SH7760/SH7763 LCDC Framebuffer driver.
72 /* en/disable the LCDC */ sh7760fb_blank()
217 /* calculate LCDC reg vals from display parameters */ sh7760fb_set_par()
249 /* shut down LCDC before changing display parameters */ sh7760fb_set_par()
422 "unusable for the LCDC\n", (unsigned long)par->fbdma); sh7760fb_alloc_mem()
H A Dsh_mobile_lcdcfb.c2 * SuperH Mobile LCDC Framebuffer
148 * struct sh_mobile_lcdc_overlay - LCDC display overlay
150 * @channel: LCDC channel this overlay belongs to
219 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
527 /* HDMI must be enabled before LCDC configuration */ sh_mobile_lcdc_display_on()
957 * __sh_mobile_lcdc_start - Configure and start the LCDC
958 * @priv: LCDC device
960 * Configure all enabled channels and start the LCDC device. All external
969 /* Enable LCDC channels. Read data from external memory, avoid using the __sh_mobile_lcdc_start()
974 /* Stop the LCDC first and disable all interrupts. */ __sh_mobile_lcdc_start()
1034 /* When using deferred I/O mode, configure the LCDC for one-shot __sh_mobile_lcdc_start()
1166 /* Start the LCDC. */ sh_mobile_lcdc_start()
1496 .id = "SH Mobile LCDC",
1721 "SH Mobile LCDC Overlay %u", ovl->index); sh_mobile_lcdc_overlay_fb_init()
1789 .id = "SH Mobile LCDC",
2051 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__); sh_mobile_lcdc_set_par()
2360 /* turn off LCDC hardware */ sh_mobile_lcdc_runtime_suspend()
2780 /* for dual channel LCDC (MAIN + SUB) force shared format setting */ sh_mobile_lcdc_probe()
2860 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
H A Dda8xx-fb.c172 * LCDC has 2 ping pong DMA channels, channel 0
271 /* Put LCDC in reset for several cycles */ lcd_enable_raster()
273 /* Write 1 to reset LCDC */ lcd_enable_raster()
277 /* Bring LCDC out of reset */ lcd_enable_raster()
429 * LCDC Version 2 adds some extra bits that increase the allowable lcd_cfg_horizontal_sync()
833 /* IRQ handler for version 2 of LCDC */ lcdc_irq_handler_rev02()
895 /* IRQ handler for version 1 LCDC */ lcdc_irq_handler_rev01()
H A Datmel_lcdfb.c370 /* Wait for the LCDC core to become idle */ atmel_lcdfb_stop_nowait()
681 /* Now, the LCDC core... */ atmel_lcdfb_set_par()
1224 /* Enable LCDC Clocks */ atmel_lcdfb_probe()
1288 /* LCDC registers */ atmel_lcdfb_probe()
1300 dev_err(dev, "cannot map LCDC registers\n"); atmel_lcdfb_probe()
1315 /* Some operations on the LCDC might sleep and atmel_lcdfb_probe()
1342 /* Power up the LCDC screen */ atmel_lcdfb_probe()
1345 dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n", atmel_lcdfb_probe()
H A Dsh_mipi_dsi.c51 /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
117 * enable LCDC data tx, transition to LPS after completion of each HS sh_mipi_dsi_enable()
H A Dsh_mobile_meram.c2 * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver
213 * LCDC cache planes allocation, init, cleanup and free
H A Dtmiofb.c141 #define LCR_LCDCCRC 0x100 /* LCDC Clock and Reset Control */
142 #define LCR_LCDCC 0x102 /* LCDC Control */
143 #define LCR_LCDCOPC 0x104 /* LCDC Output Pin Control */
H A Dsh_mobile_hdmi.c984 * until after the LCDC channel is initialized. sh_hdmi_read_edid()
985 * TODO 2: consider registering the HDMI platform device from the LCDC sh_hdmi_read_edid()
/linux-4.1.27/arch/sh/include/cpu-sh3/cpu/
H A Dsh7720.h81 /* LCDC */
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dintc-sh73a0.c42 CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC, enumerator in enum:__anon269
81 INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
131 JPU_JPEG, 0, LCRC, LCDC } },
185 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
H A Dboard-kzm9g.c286 /* LCDC */
319 .name = "LCDC",
872 /* LCDC */ kzm_init()
H A Dboard-armadillo800eva.c411 /* LCDC and backlight */
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
H A Dsetup-sh7203.c24 USB, LCDC, CMT0, CMT1, BSC, WDT, enumerator in enum:__anon2614
63 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
145 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
/linux-4.1.27/arch/avr32/mach-at32ap/include/mach/
H A Dat32ap700x.h86 /* LCDC on port C */
101 /* LCDC on port D */
121 /* LCDC on port E */
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4_kms.c285 * Setup the LCDC/LVDS path: RGB2 -> DMA_P -> LCDC -> LVDS: modeset_init()
311 dev_err(dev->dev, "failed to construct LCDC encoder\n"); modeset_init()
316 /* LCDC can be hooked to DMA_P: */ modeset_init()
/linux-4.1.27/arch/sh/include/cpu-sh2a/cpu/
H A Dsh7203.h128 /* LCDC */
/linux-4.1.27/arch/sh/include/cpu-sh4/cpu/
H A Dsh7724.h147 /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */
164 /* SCIF2 (PTE/PTF/PTN) with LCDC, VOU */
H A Dsh7722.h129 /* LCDC */
H A Dsh7723.h145 /* LCDC */
/linux-4.1.27/drivers/gpu/drm/shmobile/
H A Dshmob_drm_crtc.c157 * shmob_drm_crtc_start - Configure and start the LCDC
160 * Configure and start the LCDC device. External devices (clocks, MERAM, panels,
186 /* Reset and enable the LCDC. */ shmob_drm_crtc_start()
191 /* Stop the LCDC first and disable all interrupts. */ shmob_drm_crtc_start()
278 /* Stop the LCDC. */ shmob_drm_crtc_stop()
/linux-4.1.27/arch/sh/boards/mach-migor/
H A Dsetup.c285 .name = "LCDC",
558 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */ migor_devices_setup()
582 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */ migor_devices_setup()
H A Dlcd_qvga.c27 * Driver IC. This IC is connected to the SH7722 built-in LCDC using a
/linux-4.1.27/arch/sh/boards/mach-sh7763rdp/
H A Dsetup.c103 /* SH7763 LCDC */
/linux-4.1.27/arch/sh/boards/mach-se/7724/
H A Dsetup.c153 /* LCDC */
199 .name = "LCDC",
745 /* enable LCDC */ devices_setup()
/linux-4.1.27/arch/sh/boards/mach-ap325rxa/
H A Dsetup.c237 .name = "LCDC",
577 /* LCDC */ ap325rxa_devices_setup()
/linux-4.1.27/arch/sh/boards/mach-kfr2r09/
H A Dsetup.c174 .name = "LCDC",
576 /* setup LCDC pins for SYS panel */ kfr2r09_devices_setup()
H A Dlcd_wqvga.c27 * communicating with the main port of the LCDC using an 18-bit SYS interface.
/linux-4.1.27/arch/avr32/boards/atngw100/
H A Dmrmt.c297 /* User "alternate" LCDC inferface on Port E & D */ mrmt1_init()
H A Dsetup.c47 * end up handling here is the NAND flash, EBI pin reservation and if LCDC or
/linux-4.1.27/arch/arm/mach-imx/
H A Dmach-mx21ads.c82 /* LCDC */
/linux-4.1.27/sound/soc/sh/
H A Ddma-sh7760.c82 * *especially* when the LCDC is active). The minimum for the DMAC
/linux-4.1.27/drivers/video/fbdev/exynos/
H A Dexynos_mipi_dsi_common.c56 DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
814 /* set LCDC and CPU transfer mode to HS. */ exynos_mipi_dsi_set_hs_enable()
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dat32ap700x.c1455 * LCDC
1521 /* LCDC on port C */ at32_add_device_lcdc()
1525 /* LCDC on port D */ at32_add_device_lcdc()
1529 /* LCDC on port E */ at32_add_device_lcdc()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dmagician.c278 /* FIXME: enable LCDC here */ toppoly_lcd_power()
/linux-4.1.27/arch/sh/boards/mach-ecovec24/
H A Dsetup.c307 /* LCDC and backlight */
352 .name = "LCDC",
1148 /* enable LCDC */ arch_setup()
/linux-4.1.27/drivers/video/fbdev/omap/
H A Dsossi.c639 dev_err(fbdev->dev, "can't get LCDC IRQ\n"); sossi_init()
H A Dlcdc.c751 pr_info("omapfb: LCDC initialized\n"); omap_lcdc_init()
/linux-4.1.27/arch/arm/mach-davinci/
H A Dboard-da850-evm.c1422 pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret); da850_evm_init()
1442 pr_warn("%s: LCDC registration failed: %d\n", __func__, ret); da850_evm_init()
/linux-4.1.27/drivers/pinctrl/sh-pfc/
H A Dpfc-sh7722.c523 /* LCDC */
1015 /* LCDC */
H A Dpfc-sh7203.c1051 /* LCDC */
H A Dpfc-sh7720.c771 /* LCDC */
H A Dpfc-sh7723.c1219 /* LCDC */
H A Dpfc-sh7724.c1480 /* LCDC */

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