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Searched refs:L3 (Results 1 – 43 of 43) sorted by relevance

/linux-4.1.27/Documentation/networking/
Dipvlan.txt9 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
25 ip link add link <master-dev> <slave-dev> type ipvlan mode { l2 | L3 }
31 IPvlan has two modes of operation - L2 and L3. For a given master device,
34 that in L3 mode the slaves wont receive any multicast / broadcast traffic.
35 L3 mode is more restrictive since routing is controlled from the other (mostly)
44 4.2 L3 mode:
45 In this mode TX processing upto L3 happens on the stack instance attached
Dswitchdev.txt5 This include devices supporting L2/L3 but also various flow offloading chips,
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Domap-mcpdm.txt7 <L3 interconnect address, size>;
17 <0x49032000 0x7f>; /* L3 Interconnect */
Domap-dmic.txt7 <L3 interconnect address, size>;
17 <0x4902e000 0x7f>; /* L3 Interconnect */
Domap-mcbsp.txt10 <L3 interconnect address, size>;
/linux-4.1.27/Documentation/devicetree/bindings/arm/omap/
Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/linux-4.1.27/arch/m68k/lib/
Ddivsi3.S115 jpl L3
118 L3: movel sp@+, d2 label
Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/linux-4.1.27/Documentation/zh_CN/arm64/
Dmemory.txt88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
/linux-4.1.27/arch/alpha/kernel/
Dsetup.c1354 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1365 L3 = -1; in determine_cpu_caches()
1386 L3 = -1; in determine_cpu_caches()
1417 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1431 L3 = -1; in determine_cpu_caches()
1454 L3 = -1; in determine_cpu_caches()
1461 L3 = -1; in determine_cpu_caches()
1466 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1473 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/linux-4.1.27/drivers/cpufreq/
Ds5pv210-cpufreq.c111 L0, L1, L2, L3, L4, enumerator
129 {0, L3, 200*1000},
158 [L3] = {
373 if (index >= L3) in s5pv210_target()
Dexynos-cpufreq.h13 L0, L1, L2, L3, L4, enumerator
Dexynos4210-cpufreq.c38 {0, L3, 500 * 1000},
Dexynos5250-cpufreq.c41 {0, L3, 1400 * 1000},
Dexynos4x12-cpufreq.c39 {0, L3, 1200 * 1000},
Dexynos5440-cpufreq.c93 L0, L1, L2, L3, L4, enumerator
/linux-4.1.27/scripts/rt-tester/
Dt5-l4-pi-boost-deboost.tst83 # T3 lock L3
94 # T4 lock L3
Dt5-l4-pi-boost-deboost-setsched.tst83 # T3 lock L3
94 # T4 lock L3
/linux-4.1.27/arch/metag/tbx/
Dtbidspram.S111 $L3:
118 BR $L3
/linux-4.1.27/arch/metag/lib/
Ddiv64.S13 BNE $L3
18 $L3:
/linux-4.1.27/arch/blackfin/kernel/cplb-nompu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.1.27/arch/blackfin/kernel/cplb-mpu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.1.27/Documentation/arm64/
Dmemory.txt68 | | | | +-> [20:12] L3 index
83 | | | +----------> [28:16] L3 index
/linux-4.1.27/net/switchdev/
DKconfig11 meaning of the word "switch". This include devices supporting L2/L3 but
/linux-4.1.27/arch/xtensa/lib/
Dmemset.S91 bbci.l a4, 2, .L3
95 .L3: label
Dusercopy.S187 bbci.l a4, 2, .L3
193 .L3: label
Dmemcopy.S177 bbsi.l a4, 2, .L3
181 .L3: label
/linux-4.1.27/arch/hexagon/lib/
Dmemset.S177 if (p0.new) jump:nt .L3
189 .L3: label
/linux-4.1.27/arch/x86/kernel/cpu/
Dperf_event_intel_ds.c55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
59 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
61 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
62 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
/linux-4.1.27/Documentation/devicetree/bindings/
Dresource-names.txt28 <1 0 0x49000000 0x00001000>; /* L3 path */
/linux-4.1.27/Documentation/locking/
Drt-mutex-design.txt129 Mutexes: L1, L2, L3, L4
135 C owns L3
136 D blocked on L3
142 E->L4->D->L3->C->L2->B->L1->A
156 E->L4->D->L3->C->L2-+
175 E->L4->D->L3->C-+
239 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
240 The following shows a locking order of L1->L2->L3, but may not actually
266 mutex_lock(L3);
270 mutex_unlock(L3);
[all …]
/linux-4.1.27/arch/arm/mach-omap2/
Dsram243x.S100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
Dsram242x.S100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
/linux-4.1.27/arch/blackfin/mach-bf561/
Dsecondary.S50 L3 = r6; define
/linux-4.1.27/arch/arm/boot/dts/
Domap4.dtsi575 <0x49032000 0x7f>; /* L3 Interconnect */
588 <0x4902e000 0x7f>; /* L3 Interconnect */
600 <0x49022000 0xff>; /* L3 Interconnect */
615 <0x49024000 0xff>; /* L3 Interconnect */
630 <0x49026000 0xff>; /* L3 Interconnect */
Domap5.dtsi635 <0x49032000 0x7f>; /* L3 Interconnect */
648 <0x4902e000 0x7f>; /* L3 Interconnect */
660 <0x49022000 0xff>; /* L3 Interconnect */
675 <0x49024000 0xff>; /* L3 Interconnect */
690 <0x49026000 0xff>; /* L3 Interconnect */
Domap3-n900.dts16 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
21 * There is "unofficial" version of bootloader which enables AES in L3 firewall
23 * There is also no runtime detection code if AES is disabled in L3 firewall...
/linux-4.1.27/arch/blackfin/mach-common/
Dhead.S59 L3 = r6; define
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-devices-system-cpu166 Description: Disable L3 cache indices
172 disabled index for that node. There is one L3 structure per
177 All AMD processors with L3 caches provide this functionality.
/linux-4.1.27/Documentation/arm/SA1100/
DAssabet256 L3: Fully tested, pass.
/linux-4.1.27/drivers/net/
DKconfig155 and packets will be delivered based on the dest L3 (IPv6/IPv4 addr)
/linux-4.1.27/Documentation/
Dedac.txt59 Some architectures have ECC detectors for L1, L2 and L3 caches, along with DMA
/linux-4.1.27/Documentation/isdn/
DREADME512 isdnctrl l3_prot <InterfaceName> <L3-ProtocolName>