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Searched refs:L1_CACHE_SHIFT (Results 1 – 67 of 67) sorted by relevance

/linux-4.1.27/arch/powerpc/include/asm/
Dcache.h10 #define L1_CACHE_SHIFT 4 macro
13 #define L1_CACHE_SHIFT 6 macro
18 #define L1_CACHE_SHIFT 7 macro
20 #define L1_CACHE_SHIFT 5 macro
23 #define L1_CACHE_SHIFT 7 macro
26 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/um/include/asm/
Dcache.h6 # define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) macro
8 # define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ macro
12 # define L1_CACHE_SHIFT 5 macro
15 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/mips/include/asm/
Dcache.h14 #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT macro
15 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
17 #define SMP_CACHE_SHIFT L1_CACHE_SHIFT
/linux-4.1.27/arch/ia64/include/asm/
Dcache.h11 #define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT macro
12 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
15 # define SMP_CACHE_SHIFT L1_CACHE_SHIFT
/linux-4.1.27/arch/arc/include/asm/
Dcache.h14 #define L1_CACHE_SHIFT 6 macro
16 #define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT macro
19 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/score/include/asm/
Dcache.h4 #define L1_CACHE_SHIFT 4 macro
5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/include/asm-generic/
Dcache.h9 #define L1_CACHE_SHIFT 5 macro
10 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/m32r/include/asm/
Dcache.h5 #define L1_CACHE_SHIFT 4 macro
6 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/m68k/include/asm/
Dcache.h8 #define L1_CACHE_SHIFT 4 macro
9 #define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT)
/linux-4.1.27/arch/unicore32/include/asm/
Dcache.h15 #define L1_CACHE_SHIFT (5) macro
16 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/microblaze/include/asm/
Dcache.h18 #define L1_CACHE_SHIFT 5 macro
20 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/alpha/include/asm/
Dcache.h11 # define L1_CACHE_SHIFT 6 macro
17 # define L1_CACHE_SHIFT 5 macro
/linux-4.1.27/arch/metag/include/asm/
Dcache.h5 #define L1_CACHE_SHIFT 6 macro
6 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/hexagon/include/asm/
Dcache.h25 #define L1_CACHE_SHIFT (5) macro
26 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/frv/include/asm/
Dcache.h17 #define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT) macro
18 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/arm/include/asm/
Dcache.h7 #define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT macro
8 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
Dmemory.h143 #define ARCH_PGD_SHIFT L1_CACHE_SHIFT
/linux-4.1.27/arch/arm64/include/asm/
Dcache.h21 #define L1_CACHE_SHIFT 6 macro
22 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/x86/include/asm/
Dcache.h7 #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) macro
8 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/avr32/include/asm/
Dcache.h4 #define L1_CACHE_SHIFT 5 macro
5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/tile/include/asm/
Dcache.h21 #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() macro
22 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/blackfin/include/asm/
Dcache.h16 #define L1_CACHE_SHIFT 5 macro
17 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/parisc/include/asm/
Dcache.h19 #define L1_CACHE_SHIFT 6 macro
22 #define L1_CACHE_SHIFT 5 macro
/linux-4.1.27/arch/c6x/include/asm/
Dcache.h38 #define L1_CACHE_SHIFT L2_CACHE_SHIFT macro
39 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/blackfin/mach-common/
Dcache.S43 R2 >>= L1_CACHE_SHIFT;
122 P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
/linux-4.1.27/arch/arm/mach-tegra/
Dreset-handler.S95 .align L1_CACHE_SHIFT
118 .align L1_CACHE_SHIFT
277 .align L1_CACHE_SHIFT
288 .align L1_CACHE_SHIFT
Dsleep.S125 .align L1_CACHE_SHIFT
Dsleep-tegra20.S322 .align L1_CACHE_SHIFT
576 .align L1_CACHE_SHIFT
Dsleep-tegra30.S304 .align L1_CACHE_SHIFT
536 .align L1_CACHE_SHIFT
827 .align L1_CACHE_SHIFT
/linux-4.1.27/arch/cris/include/arch-v10/arch/
Dcache.h6 #define L1_CACHE_SHIFT 5 macro
/linux-4.1.27/arch/openrisc/include/asm/
Dcache.h27 #define L1_CACHE_SHIFT 4 macro
/linux-4.1.27/arch/s390/include/asm/
Dcache.h13 #define L1_CACHE_SHIFT 8 macro
/linux-4.1.27/include/net/netns/
Dhash.h16 return (u32)(((unsigned long)net) >> L1_CACHE_SHIFT); in net_hash_mix()
/linux-4.1.27/arch/sparc/include/asm/
Dcache.h12 #define L1_CACHE_SHIFT 5 macro
/linux-4.1.27/arch/nios2/include/asm/
Dcache.h28 #define L1_CACHE_SHIFT NIOS2_ICACHE_LINE_SHIFT macro
/linux-4.1.27/arch/sh/include/asm/
Dcache.h15 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/linux-4.1.27/arch/sh/include/cpu-sh2/cpu/
Dcache.h13 #define L1_CACHE_SHIFT 4 macro
/linux-4.1.27/arch/mn10300/proc-mn103e010/include/proc/
Dcache.h19 #define L1_CACHE_SHIFT 4 /* shift for bytes per entry */ macro
/linux-4.1.27/arch/mn10300/proc-mn2ws0050/include/proc/
Dcache.h25 #define L1_CACHE_SHIFT 5 /* shift for bytes per entry */ macro
/linux-4.1.27/arch/cris/include/arch-v32/arch/
Dcache.h8 #define L1_CACHE_SHIFT 5 macro
/linux-4.1.27/arch/sh/include/cpu-sh3/cpu/
Dcache.h13 #define L1_CACHE_SHIFT 4 macro
/linux-4.1.27/arch/xtensa/include/asm/
Dcache.h16 #define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH macro
/linux-4.1.27/arch/sh/include/cpu-sh4/cpu/
Dcache.h13 #define L1_CACHE_SHIFT 5 macro
/linux-4.1.27/arch/sh/include/cpu-sh2a/cpu/
Dcache.h13 #define L1_CACHE_SHIFT 4 macro
/linux-4.1.27/arch/sh/include/cpu-sh5/cpu/
Dcache.h15 #define L1_CACHE_SHIFT 5 macro
/linux-4.1.27/include/linux/
Dcache.h51 #define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
/linux-4.1.27/arch/mn10300/mm/
Dcache-flush-by-reg.S126 lsr L1_CACHE_SHIFT,d3
259 lsr L1_CACHE_SHIFT,d3
Dcache-inv-by-tag.S163 lsr L1_CACHE_SHIFT,d1 # total number of entries to
/linux-4.1.27/lib/
Datomic64.c44 addr >>= L1_CACHE_SHIFT; in lock_addr()
Ddma-debug.c460 #define CACHELINE_PER_PAGE_SHIFT (PAGE_SHIFT - L1_CACHE_SHIFT)
466 (entry->offset >> L1_CACHE_SHIFT); in to_cacheline_number()
/linux-4.1.27/arch/ia64/include/asm/sn/
Dbte.h42 #define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT)
/linux-4.1.27/arch/arm64/lib/
Dmemcpy.S171 .p2align L1_CACHE_SHIFT
Dmemmove.S167 .p2align L1_CACHE_SHIFT
Dmemset.S129 .p2align L1_CACHE_SHIFT
/linux-4.1.27/arch/powerpc/kernel/
Dmisc_32.S357 srwi. r4,r4,L1_CACHE_SHIFT
391 srwi. r4,r4,L1_CACHE_SHIFT
412 srwi. r4,r4,L1_CACHE_SHIFT
434 srwi. r4,r4,L1_CACHE_SHIFT
Dvdso.c776 vdso_data->dcache_log_block_size = L1_CACHE_SHIFT; in vdso_init()
778 vdso_data->icache_log_block_size = L1_CACHE_SHIFT; in vdso_init()
/linux-4.1.27/fs/
Ddcookies.c61 return (dcookie >> L1_CACHE_SHIFT) & (hash_size - 1); in dcookie_hash()
/linux-4.1.27/arch/ia64/sn/kernel/
Dbte.c186 transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK); in bte_copy()
/linux-4.1.27/arch/sh/kernel/cpu/sh3/
Dentry.S504 .align L1_CACHE_SHIFT
/linux-4.1.27/arch/powerpc/lib/
Dcopy_32.S69 LG_CACHELINE_BYTES = L1_CACHE_SHIFT
/linux-4.1.27/arch/arm64/kernel/
Dhead.S618 .align L1_CACHE_SHIFT
/linux-4.1.27/drivers/parisc/
Dsba_iommu.c645 entries_per_cacheline = L1_CACHE_SHIFT - 3; in sba_mark_invalid()
/linux-4.1.27/drivers/net/
Dmacvlan.c218 return (u32)(((unsigned long)vlan) >> L1_CACHE_SHIFT); in macvlan_hash_mix()
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x.h1487 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
/linux-4.1.27/fs/quota/
Ddquot.c259 tmp = (((unsigned long)sb>>L1_CACHE_SHIFT) ^ id) * (MAXQUOTAS - type); in hashfn()
/linux-4.1.27/fs/reiserfs/
Dreiserfs.h2808 (((unsigned long)sb>>L1_CACHE_SHIFT) ^ \
/linux-4.1.27/drivers/net/ethernet/broadcom/
Dcnic.c5025 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT; in cnic_init_bnx2x_rx_ring()