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Searched refs:IO_IRQ_BASE (Results 1 – 4 of 4) sorted by relevance

/linux-4.1.27/drivers/irqchip/
Dirq-zevio.c31 #define IO_IRQ_BASE 0x000 macro
98 zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE); in zevio_of_init()
115 gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
116 gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
117 gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE; in zevio_of_init()
118 gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET; in zevio_of_init()
/linux-4.1.27/arch/mips/include/asm/dec/
Dioasic_ints.h66 #define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */ macro
69 #define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE)
/linux-4.1.27/arch/mips/dec/
Dint-handler.S235 li a0,IO_IRQ_BASE
244 li a0,IO_IRQ_BASE+IO_INR_DMA
Dsetup.c514 init_ioasic_irqs(IO_IRQ_BASE); in dec_init_kn02ba()
611 init_ioasic_irqs(IO_IRQ_BASE); in dec_init_kn02ca()
712 init_ioasic_irqs(IO_IRQ_BASE); in dec_init_kn03()