/linux-4.1.27/drivers/video/fbdev/intelfb/ |
H A D | intelfbhw.c | 284 if (INREG(LVDS) & PORT_ENABLE) intelfbhw_check_non_crt() 286 if (INREG(DVOA) & PORT_ENABLE) intelfbhw_check_non_crt() 288 if (INREG(DVOB) & PORT_ENABLE) intelfbhw_check_non_crt() 290 if (INREG(DVOC) & PORT_ENABLE) intelfbhw_check_non_crt() 425 tmp = INREG(DSPACNTR); intelfbhw_do_blank() 432 tmp = INREG(DSPABASE); intelfbhw_do_blank() 449 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; intelfbhw_do_blank() 529 hw->vga0_divisor = INREG(VGA0_DIVISOR); intelfbhw_read_hw_state() 530 hw->vga1_divisor = INREG(VGA1_DIVISOR); intelfbhw_read_hw_state() 531 hw->vga_pd = INREG(VGAPD); intelfbhw_read_hw_state() 532 hw->dpll_a = INREG(DPLL_A); intelfbhw_read_hw_state() 533 hw->dpll_b = INREG(DPLL_B); intelfbhw_read_hw_state() 534 hw->fpa0 = INREG(FPA0); intelfbhw_read_hw_state() 535 hw->fpa1 = INREG(FPA1); intelfbhw_read_hw_state() 536 hw->fpb0 = INREG(FPB0); intelfbhw_read_hw_state() 537 hw->fpb1 = INREG(FPB1); intelfbhw_read_hw_state() 545 hw->palette_a[i] = INREG(PALETTE_A + (i << 2)); intelfbhw_read_hw_state() 546 hw->palette_b[i] = INREG(PALETTE_B + (i << 2)); intelfbhw_read_hw_state() 553 hw->htotal_a = INREG(HTOTAL_A); intelfbhw_read_hw_state() 554 hw->hblank_a = INREG(HBLANK_A); intelfbhw_read_hw_state() 555 hw->hsync_a = INREG(HSYNC_A); intelfbhw_read_hw_state() 556 hw->vtotal_a = INREG(VTOTAL_A); intelfbhw_read_hw_state() 557 hw->vblank_a = INREG(VBLANK_A); intelfbhw_read_hw_state() 558 hw->vsync_a = INREG(VSYNC_A); intelfbhw_read_hw_state() 559 hw->src_size_a = INREG(SRC_SIZE_A); intelfbhw_read_hw_state() 560 hw->bclrpat_a = INREG(BCLRPAT_A); intelfbhw_read_hw_state() 561 hw->htotal_b = INREG(HTOTAL_B); intelfbhw_read_hw_state() 562 hw->hblank_b = INREG(HBLANK_B); intelfbhw_read_hw_state() 563 hw->hsync_b = INREG(HSYNC_B); intelfbhw_read_hw_state() 564 hw->vtotal_b = INREG(VTOTAL_B); intelfbhw_read_hw_state() 565 hw->vblank_b = INREG(VBLANK_B); intelfbhw_read_hw_state() 566 hw->vsync_b = INREG(VSYNC_B); intelfbhw_read_hw_state() 567 hw->src_size_b = INREG(SRC_SIZE_B); intelfbhw_read_hw_state() 568 hw->bclrpat_b = INREG(BCLRPAT_B); intelfbhw_read_hw_state() 573 hw->adpa = INREG(ADPA); intelfbhw_read_hw_state() 574 hw->dvoa = INREG(DVOA); intelfbhw_read_hw_state() 575 hw->dvob = INREG(DVOB); intelfbhw_read_hw_state() 576 hw->dvoc = INREG(DVOC); intelfbhw_read_hw_state() 577 hw->dvoa_srcdim = INREG(DVOA_SRCDIM); intelfbhw_read_hw_state() 578 hw->dvob_srcdim = INREG(DVOB_SRCDIM); intelfbhw_read_hw_state() 579 hw->dvoc_srcdim = INREG(DVOC_SRCDIM); intelfbhw_read_hw_state() 580 hw->lvds = INREG(LVDS); intelfbhw_read_hw_state() 585 hw->pipe_a_conf = INREG(PIPEACONF); intelfbhw_read_hw_state() 586 hw->pipe_b_conf = INREG(PIPEBCONF); intelfbhw_read_hw_state() 587 hw->disp_arb = INREG(DISPARB); intelfbhw_read_hw_state() 592 hw->cursor_a_control = INREG(CURSOR_A_CONTROL); intelfbhw_read_hw_state() 593 hw->cursor_b_control = INREG(CURSOR_B_CONTROL); intelfbhw_read_hw_state() 594 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); intelfbhw_read_hw_state() 595 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); intelfbhw_read_hw_state() 601 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); intelfbhw_read_hw_state() 602 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); intelfbhw_read_hw_state() 608 hw->cursor_size = INREG(CURSOR_SIZE); intelfbhw_read_hw_state() 613 hw->disp_a_ctrl = INREG(DSPACNTR); intelfbhw_read_hw_state() 614 hw->disp_b_ctrl = INREG(DSPBCNTR); intelfbhw_read_hw_state() 615 hw->disp_a_base = INREG(DSPABASE); intelfbhw_read_hw_state() 616 hw->disp_b_base = INREG(DSPBBASE); intelfbhw_read_hw_state() 617 hw->disp_a_stride = INREG(DSPASTRIDE); intelfbhw_read_hw_state() 618 hw->disp_b_stride = INREG(DSPBSTRIDE); intelfbhw_read_hw_state() 623 hw->vgacntrl = INREG(VGACNTRL); intelfbhw_read_hw_state() 628 hw->add_id = INREG(ADD_ID); intelfbhw_read_hw_state() 634 hw->swf0x[i] = INREG(SWF00 + (i << 2)); intelfbhw_read_hw_state() 635 hw->swf1x[i] = INREG(SWF10 + (i << 2)); intelfbhw_read_hw_state() 637 hw->swf3x[i] = INREG(SWF30 + (i << 2)); intelfbhw_read_hw_state() 641 hw->fence[i] = INREG(FENCE + (i << 2)); intelfbhw_read_hw_state() 643 hw->instpm = INREG(INSTPM); intelfbhw_read_hw_state() 644 hw->mem_mode = INREG(MEM_MODE); intelfbhw_read_hw_state() 645 hw->fw_blc_0 = INREG(FW_BLC_0); intelfbhw_read_hw_state() 646 hw->fw_blc_1 = INREG(FW_BLC_1); intelfbhw_read_hw_state() 1299 tmp = INREG(VGACNTRL); intelfbhw_program_mode() 1356 tmp = INREG(pipe_conf_reg); intelfbhw_program_mode() 1362 tmp_val[count % 3] = INREG(PIPEA_DSL); intelfbhw_program_mode() 1368 tmp = INREG(pipe_conf_reg); intelfbhw_program_mode() 1374 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE); intelfbhw_program_mode() 1377 tmp = INREG(DSPACNTR); intelfbhw_program_mode() 1380 tmp = INREG(DSPBCNTR); intelfbhw_program_mode() 1387 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE); intelfbhw_program_mode() 1388 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE); intelfbhw_program_mode() 1389 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE); intelfbhw_program_mode() 1392 tmp = INREG(ADPA); intelfbhw_program_mode() 1401 tmp = INREG(dpll_reg); intelfbhw_program_mode() 1420 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE); intelfbhw_program_mode() 1447 tmp = INREG(ADPA); intelfbhw_program_mode() 1459 tmp = INREG(DSPACNTR); intelfbhw_program_mode() 1475 tmp = INREG(DSPACNTR); intelfbhw_program_mode() 1511 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; wait_ring() 1519 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; wait_ring() 1582 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; refresh_ring() 1583 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; refresh_ring() 1600 tmp = INREG(PRI_RING_LENGTH); reset_state() 1850 tmp = INREG(CURSOR_A_CONTROL); intelfbhw_cursor_init() 1858 tmp = INREG(CURSOR_CONTROL); intelfbhw_cursor_init() 1882 tmp = INREG(CURSOR_A_CONTROL); intelfbhw_cursor_hide() 1889 tmp = INREG(CURSOR_CONTROL); intelfbhw_cursor_hide() 1911 tmp = INREG(CURSOR_A_CONTROL); intelfbhw_cursor_show() 1918 tmp = INREG(CURSOR_CONTROL); intelfbhw_cursor_show() 2027 OUTREG(PIPEASTAT, INREG(PIPEASTAT)); intelfbhw_irq()
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H A D | intelfb_i2c.c | 62 val = INREG(chan->reg); intelfb_gpio_setscl() 73 val = INREG(chan->reg); intelfb_gpio_setsda() 84 val = INREG(chan->reg); intelfb_gpio_getscl() 96 val = INREG(chan->reg); intelfb_gpio_getsda()
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H A D | intelfbhw.h | 525 #define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr))) macro 553 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \ 554 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
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H A D | intelfbdrv.c | 1372 OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); intelfb_set_par() 1593 if (INREG(CURSOR_A_BASEADDR) != physical) { intelfb_cursor()
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/linux-4.1.27/drivers/video/fbdev/aty/ |
H A D | radeon_i2c.c | 23 val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN); radeon_gpio_setscl() 28 (void)INREG(chan->ddc_reg); radeon_gpio_setscl() 37 val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN); radeon_gpio_setsda() 42 (void)INREG(chan->ddc_reg); radeon_gpio_setsda() 51 val = INREG(chan->ddc_reg); radeon_gpio_getscl() 62 val = INREG(chan->ddc_reg); radeon_gpio_getsda() 156 (INREG(LVDS_GEN_CNTL) & LVDS_ON)) { radeon_probe_i2c_connector()
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H A D | radeon_pm.c | 338 if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13) radeon_pm_enable_dynamic_mode() 421 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) radeon_pm_enable_dynamic_mode() 473 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) || radeon_pm_enable_dynamic_mode() 475 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) { radeon_pm_enable_dynamic_mode() 491 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) radeon_pm_enable_dynamic_mode() 502 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) { radeon_pm_enable_dynamic_mode() 558 return INREG( MC_IND_DATA); INMC() 573 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); radeon_pm_save_regs() 574 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); radeon_pm_save_regs() 575 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); radeon_pm_save_regs() 576 rinfo->save_regs[13] = INREG(TV_DAC_CNTL); radeon_pm_save_regs() 577 rinfo->save_regs[14] = INREG(BUS_CNTL1); radeon_pm_save_regs() 578 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL); radeon_pm_save_regs() 579 rinfo->save_regs[16] = INREG(AGP_CNTL); radeon_pm_save_regs() 580 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000; radeon_pm_save_regs() 581 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000; radeon_pm_save_regs() 582 rinfo->save_regs[19] = INREG(GPIOPAD_A); radeon_pm_save_regs() 583 rinfo->save_regs[20] = INREG(GPIOPAD_EN); radeon_pm_save_regs() 584 rinfo->save_regs[21] = INREG(GPIOPAD_MASK); radeon_pm_save_regs() 585 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A); radeon_pm_save_regs() 586 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN); radeon_pm_save_regs() 587 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK); radeon_pm_save_regs() 588 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC); radeon_pm_save_regs() 589 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC); radeon_pm_save_regs() 590 rinfo->save_regs[27] = INREG(GPIO_MONID); radeon_pm_save_regs() 591 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC); radeon_pm_save_regs() 593 rinfo->save_regs[29] = INREG(SURFACE_CNTL); radeon_pm_save_regs() 594 rinfo->save_regs[30] = INREG(MC_FB_LOCATION); radeon_pm_save_regs() 595 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR); radeon_pm_save_regs() 596 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION); radeon_pm_save_regs() 597 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR); radeon_pm_save_regs() 600 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG); radeon_pm_save_regs() 601 rinfo->save_regs[36] = INREG(BUS_CNTL); radeon_pm_save_regs() 602 rinfo->save_regs[39] = INREG(RBBM_CNTL); radeon_pm_save_regs() 603 rinfo->save_regs[40] = INREG(DAC_CNTL); radeon_pm_save_regs() 604 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL); radeon_pm_save_regs() 605 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG); radeon_pm_save_regs() 606 rinfo->save_regs[38] = INREG(FCP_CNTL); radeon_pm_save_regs() 609 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL); radeon_pm_save_regs() 615 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL); radeon_pm_save_regs() 619 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL); radeon_pm_save_regs() 620 rinfo->save_regs[46] = INREG(MC_CNTL); radeon_pm_save_regs() 621 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER); radeon_pm_save_regs() 622 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER); radeon_pm_save_regs() 623 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL); radeon_pm_save_regs() 624 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB); radeon_pm_save_regs() 625 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL); radeon_pm_save_regs() 626 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB); radeon_pm_save_regs() 627 rinfo->save_regs[53] = INREG(MC_DEBUG); radeon_pm_save_regs() 629 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL); radeon_pm_save_regs() 630 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL); radeon_pm_save_regs() 631 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC); radeon_pm_save_regs() 632 rinfo->save_regs[57] = INREG(FW_CNTL); radeon_pm_save_regs() 666 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL); radeon_pm_save_regs() 668 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR); radeon_pm_save_regs() 669 rinfo->save_regs[82] = INREG(FP_GEN_CNTL); radeon_pm_save_regs() 670 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL); radeon_pm_save_regs() 671 rinfo->save_regs[84] = INREG(TMDS_CNTL); radeon_pm_save_regs() 672 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL); radeon_pm_save_regs() 673 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL); radeon_pm_save_regs() 674 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG); radeon_pm_save_regs() 675 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL); radeon_pm_save_regs() 679 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL); radeon_pm_save_regs() 680 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL); radeon_pm_save_regs() 681 rinfo->save_regs[96] = INREG(HDP_DEBUG); radeon_pm_save_regs() 781 reg = INREG(BUS_CNTL1); radeon_pm_low_current() 797 reg = INREG(TV_DAC_CNTL); radeon_pm_low_current() 804 reg = INREG(TMDS_TRANSMITTER_CNTL); radeon_pm_low_current() 808 reg = INREG(DAC_CNTL); radeon_pm_low_current() 812 reg = INREG(DAC_CNTL2); radeon_pm_low_current() 816 reg = INREG(TV_DAC_CNTL); radeon_pm_low_current() 910 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & radeon_pm_setup_for_suspend() 963 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); radeon_pm_setup_for_suspend() 965 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK) radeon_pm_setup_for_suspend() 968 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1)); radeon_pm_setup_for_suspend() 969 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000); radeon_pm_setup_for_suspend() 974 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) radeon_pm_setup_for_suspend() 983 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK)) radeon_pm_setup_for_suspend() 992 disp_mis_cntl = INREG(DISP_MISC_CNTL); radeon_pm_setup_for_suspend() 1009 disp_pwr_man = INREG(DISP_PWR_MAN); radeon_pm_setup_for_suspend() 1034 disp_pwr_man = INREG(DISP_PWR_MAN); radeon_pm_setup_for_suspend() 1050 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) radeon_pm_setup_for_suspend() 1052 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) radeon_pm_setup_for_suspend() 1104 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG); radeon_pm_program_mode_reg() 1127 } while ((INREG(MC_STATUS) radeon_pm_program_mode_reg() 1139 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A radeon_pm_m10_program_mode_wait() 1204 mc = INREG(MC_CNTL); radeon_pm_enable_dll_m10() 1249 crtcGenCntl = INREG( CRTC_GEN_CNTL); radeon_pm_full_reset_sdram() 1250 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL); radeon_pm_full_reset_sdram() 1252 crtc_more_cntl = INREG( CRTC_MORE_CNTL); radeon_pm_full_reset_sdram() 1253 fp_gen_cntl = INREG( FP_GEN_CNTL); radeon_pm_full_reset_sdram() 1254 fp2_gen_cntl = INREG( FP2_GEN_CNTL); radeon_pm_full_reset_sdram() 1282 memRefreshCntl = INREG( MEM_REFRESH_CNTL) radeon_pm_full_reset_sdram() 1328 memRefreshCntl = INREG( MEM_REFRESH_CNTL) radeon_pm_full_reset_sdram() 1336 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); radeon_pm_full_reset_sdram() 1343 INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); radeon_pm_full_reset_sdram() 1351 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20); radeon_pm_full_reset_sdram() 1356 INREG( MEM_SDRAM_MODE_REG) radeon_pm_full_reset_sdram() 1374 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); radeon_pm_full_reset_sdram() 1382 memRefreshCntl = INREG( MEM_REFRESH_CNTL) radeon_pm_full_reset_sdram() 1389 INREG( MEM_SDRAM_MODE_REG) radeon_pm_full_reset_sdram() 1415 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); radeon_pm_full_reset_sdram() 1438 INREG(PAD_CTLR_STRENGTH); radeon_pm_reset_pad_ctlr_strength() 1439 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE); radeon_pm_reset_pad_ctlr_strength() 1440 tmp = INREG(PAD_CTLR_STRENGTH); radeon_pm_reset_pad_ctlr_strength() 1443 tmp2 = INREG(PAD_CTLR_STRENGTH); radeon_pm_reset_pad_ctlr_strength() 1559 r2ec = INREG(VGA_DDA_ON_OFF); radeon_pm_m10_disable_spread_spectrum() 1586 r2ec = INREG(VGA_DDA_ON_OFF); radeon_pm_m10_enable_lvds_spread_spectrum() 1610 tmp = INREG(LVDS_GEN_CNTL); radeon_pm_m10_enable_lvds_spread_spectrum() 1614 tmp = INREG(LVDS_PLL_CNTL); radeon_pm_m10_enable_lvds_spread_spectrum() 1623 INREG(RBBM_STATUS); radeon_pm_m10_enable_lvds_spread_spectrum() 1737 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); radeon_reinitialize_M10() 1738 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); radeon_reinitialize_M10() 1741 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); radeon_reinitialize_M10() 1753 INREG(SURFACE_CNTL); radeon_reinitialize_M10() 1759 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; radeon_reinitialize_M10() 1763 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; radeon_reinitialize_M10() 1789 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL) radeon_reinitialize_M10() 1791 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL) radeon_reinitialize_M10() 1796 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) radeon_reinitialize_M10() 1895 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); radeon_reinitialize_M10() 1898 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); radeon_reinitialize_M10() 1903 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); radeon_reinitialize_M10() 1927 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); radeon_reinitialize_M10() 1992 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); radeon_reinitialize_M9P() 2004 INREG(SURFACE_CNTL); radeon_reinitialize_M9P() 2010 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; radeon_reinitialize_M9P() 2014 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; radeon_reinitialize_M9P() 2036 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) radeon_reinitialize_M9P() 2127 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); radeon_reinitialize_M9P() 2130 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); radeon_reinitialize_M9P() 2135 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); radeon_reinitialize_M9P() 2166 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON); radeon_reinitialize_M9P() 2196 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); radeon_reinitialize_M9P() 2226 INREG(PAD_CTLR_STRENGTH); 2227 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000); 2230 INREG(PAD_CTLR_STRENGTH); 2233 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000); 2234 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100); 2235 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)); 2237 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)); 2238 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000); 2250 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL)); 2375 INREG(FP_GEN_CNTL); 2377 tmp = INREG(FP_GEN_CNTL); 2381 tmp = INREG(DISP_OUTPUT_CNTL); 2409 tmp = INREG(FP_GEN_CNTL); 2410 tmp2 = INREG(TMDS_TRANSMITTER_CNTL); 2420 tmp = INREG(CRTC_MORE_CNTL); 2423 cgc = INREG(CRTC_GEN_CNTL); 2424 cec = INREG(CRTC_EXT_CNTL); 2425 c2gc = INREG(CRTC2_GEN_CNTL); 2458 tmp = INREG(CLOCK_CNTL_INDEX); 2492 tmp2 = INREG(FP_GEN_CNTL); 2493 tmp = INREG(TMDS_TRANSMITTER_CNTL); 2508 cgc = INREG(CRTC_GEN_CNTL); 2683 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN)); radeonfb_pci_suspend() 2685 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON)); radeonfb_pci_suspend() 2686 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000); radeonfb_pci_suspend() 2688 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON)); radeonfb_pci_suspend() 2881 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000); radeonfb_pm_init()
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H A D | radeon_accel.c | 29 local_base = INREG(MC_FB_LOCATION) << 16; radeon_fixup_offset() 200 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); radeonfb_engine_reset() 211 host_path_cntl = INREG(HOST_PATH_CNTL); radeonfb_engine_reset() 212 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); radeonfb_engine_reset() 221 INREG(RBBM_SOFT_RESET); radeonfb_engine_reset() 223 tmp = INREG(RB2D_DSTCACHE_MODE); radeonfb_engine_reset() 234 INREG(RBBM_SOFT_RESET); radeonfb_engine_reset() 243 INREG(RBBM_SOFT_RESET); radeonfb_engine_reset() 247 INREG(HOST_PATH_CNTL); radeonfb_engine_reset() 268 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | radeonfb_engine_init() 284 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; radeonfb_engine_init()
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H A D | radeonfb.h | 392 #define INREG(addr) readl((rinfo->mmio_base)+addr) macro 402 tmp = INREG(addr); _OUTREGP() 433 (void)INREG(CLOCK_CNTL_DATA); radeon_pll_errata_after_index() 434 (void)INREG(CRTC_GEN_CNTL); radeon_pll_errata_after_index() 445 save = INREG(CLOCK_CNTL_INDEX); radeon_pll_errata_after_data() 448 tmp = INREG(CLOCK_CNTL_DATA); radeon_pll_errata_after_data() 459 data = INREG(CLOCK_CNTL_DATA); __INPLL() 540 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) _radeon_fifo_wait() 562 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) radeon_engine_flush() 578 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { _radeon_engine_idle()
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H A D | radeon_base.c | 310 temp = INREG(MPP_TB_CONFIG); radeon_map_ROM() 314 temp = INREG(MPP_TB_CONFIG); radeon_map_ROM() 478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) radeon_probe_pll_params() 484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) radeon_probe_pll_params() 488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) radeon_probe_pll_params() 504 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; radeon_probe_pll_params() 505 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); radeon_probe_pll_params() 882 tmp = INREG(LVDS_GEN_CNTL); radeonfb_ioctl() 886 tmp = INREG(LVDS_GEN_CNTL); radeonfb_ioctl() 894 tmp = INREG(CRTC_EXT_CNTL); radeonfb_ioctl() 899 tmp = INREG(CRTC_EXT_CNTL); radeonfb_ioctl() 912 tmp = INREG(LVDS_GEN_CNTL); radeonfb_ioctl() 916 tmp = INREG(CRTC_EXT_CNTL); radeonfb_ioctl() 940 val = INREG(CRTC_EXT_CNTL); radeon_screen_blank() 977 val = INREG(LVDS_GEN_CNTL); radeon_screen_blank() 1139 dac_cntl2 = INREG(DAC_CNTL2); radeonfb_setcolreg() 1169 dac_cntl2 = INREG(DAC_CNTL2); radeonfb_setcmap() 1205 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); radeon_save_state() 1206 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); radeon_save_state() 1207 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); radeon_save_state() 1208 save->dac_cntl = INREG(DAC_CNTL); radeon_save_state() 1209 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); radeon_save_state() 1210 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); radeon_save_state() 1211 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); radeon_save_state() 1212 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); radeon_save_state() 1213 save->crtc_pitch = INREG(CRTC_PITCH); radeon_save_state() 1214 save->surface_cntl = INREG(SURFACE_CNTL); radeon_save_state() 1217 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); radeon_save_state() 1218 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); radeon_save_state() 1219 save->fp_gen_cntl = INREG(FP_GEN_CNTL); radeon_save_state() 1220 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); radeon_save_state() 1221 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); radeon_save_state() 1222 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); radeon_save_state() 1223 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); radeon_save_state() 1224 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); radeon_save_state() 1225 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); radeon_save_state() 1226 save->tmds_crc = INREG(TMDS_CRC); radeon_save_state() 1227 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); radeon_save_state() 1231 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; radeon_save_state() 1448 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL); radeon_calc_pll_regs() 1464 disp_output_cntl = INREG(DISP_OUTPUT_CNTL); radeon_calc_pll_regs() 1649 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | radeonfb_set_par() 1924 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); fixup_memory_mappings() 1927 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); fixup_memory_mappings() 1928 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); fixup_memory_mappings() 1934 aper_base = INREG(CNFG_APER_0_BASE); fixup_memory_mappings() 1935 aper_size = INREG(CNFG_APER_SIZE); fixup_memory_mappings() 2001 u32 tom = INREG(NB_TOM); radeon_identify_vram() 2011 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); radeon_identify_vram() 2022 tmp = INREG(CNFG_MEMSIZE); radeon_identify_vram() 2048 (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) radeon_identify_vram() 2053 tmp = INREG(MEM_CNTL); radeon_identify_vram() 2219 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; radeonfb_pci_register() 2226 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) radeonfb_pci_register()
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H A D | radeon_monitor.c | 324 ulOrigCRTC_EXT_CNTL = INREG(CRTC_EXT_CNTL); radeon_crt_is_connected() 329 ulOrigDAC_EXT_CNTL = INREG(DAC_EXT_CNTL); radeon_crt_is_connected() 343 ulOrigDAC_CNTL = INREG(DAC_CNTL); radeon_crt_is_connected() 353 ulData = INREG(DAC_CNTL); radeon_crt_is_connected() 568 ((rinfo->bios_seg && (INREG(BIOS_4_SCRATCH) & 4)) radeon_probe_screens() 569 || (INREG(LVDS_GEN_CNTL) & LVDS_ON))) { radeon_probe_screens() 851 u32 tmp = INREG(FP_HORZ_STRETCH) & HORZ_PANEL_SIZE; radeon_check_modes() 853 tmp = INREG(FP_VERT_STRETCH) & VERT_PANEL_SIZE; radeon_check_modes()
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H A D | radeon_backlight.c | 72 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); radeon_bl_update_status()
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/linux-4.1.27/drivers/gpu/drm/i915/ |
H A D | i915_reg.h | 4384 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4386 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4388 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
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