Searched refs:IMX6SL_CLK_PLL5_POST_DIV (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dimx6sl-clock.h28 #define IMX6SL_CLK_PLL5_POST_DIV 15 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dimx6sl-clock.h28 #define IMX6SL_CLK_PLL5_POST_DIV 15 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dimx6sl-clock.h28 #define IMX6SL_CLK_PLL5_POST_DIV 15 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dimx6sl-clock.h28 #define IMX6SL_CLK_PLL5_POST_DIV 15 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dimx6sl-clock.h28 #define IMX6SL_CLK_PLL5_POST_DIV 15 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dimx6sl-clock.h28 #define IMX6SL_CLK_PLL5_POST_DIV 15 macro
/linux-4.1.27/arch/arm/mach-imx/
H A Dclk-imx6sl.c267 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()

Completed in 90 milliseconds