/linux-4.1.27/drivers/isdn/hisax/ |
H A D | hscx.h | 35 #define HSCX_MASK 0x20 macro
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H A D | avm_a1p.c | 164 WriteHSCX(cs, 0, HSCX_MASK, 0xff); avm_a1p_interrupt() 165 WriteHSCX(cs, 1, HSCX_MASK, 0xff); avm_a1p_interrupt() 168 WriteHSCX(cs, 0, HSCX_MASK, 0x00); avm_a1p_interrupt() 169 WriteHSCX(cs, 1, HSCX_MASK, 0x00); avm_a1p_interrupt()
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H A D | hscx.c | 239 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF); clear_pending_hscx_ints() 240 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF); clear_pending_hscx_ints() 272 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0); inithscxisac() 273 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0); inithscxisac()
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H A D | ix1_micro.c | 154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); ix1micro_interrupt() 155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); ix1micro_interrupt() 158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); ix1micro_interrupt() 159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); ix1micro_interrupt()
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H A D | mic.c | 148 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF); mic_interrupt() 149 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF); mic_interrupt() 152 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0); mic_interrupt() 153 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0); mic_interrupt()
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H A D | s0box.c | 175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); s0box_interrupt() 176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); s0box_interrupt() 179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); s0box_interrupt() 180 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); s0box_interrupt()
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H A D | saphir.c | 151 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); saphir_interrupt() 152 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); saphir_interrupt() 155 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); saphir_interrupt() 156 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); saphir_interrupt()
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H A D | telespci.c | 248 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); telespci_interrupt() 249 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); telespci_interrupt() 252 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); telespci_interrupt() 253 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); telespci_interrupt()
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H A D | avm_a1.c | 127 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); avm_a1_interrupt() 128 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); avm_a1_interrupt() 131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); avm_a1_interrupt() 132 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); avm_a1_interrupt()
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H A D | niccy.c | 162 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); niccy_interrupt() 163 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, niccy_interrupt() 167 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); niccy_interrupt() 168 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0); niccy_interrupt()
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H A D | teles0.c | 174 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); teles0_interrupt() 175 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); teles0_interrupt() 178 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); teles0_interrupt() 179 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); teles0_interrupt()
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H A D | asuscom.c | 184 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF); asuscom_interrupt() 185 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF); asuscom_interrupt() 188 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0x0); asuscom_interrupt() 189 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0x0); asuscom_interrupt()
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H A D | teles3.c | 135 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); teles3_interrupt() 136 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); teles3_interrupt() 139 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); teles3_interrupt() 140 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); teles3_interrupt()
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H A D | gazel.c | 264 WriteHSCX(cs, 0, HSCX_MASK, 0xFF); gazel_interrupt() 265 WriteHSCX(cs, 1, HSCX_MASK, 0xFF); gazel_interrupt() 268 WriteHSCX(cs, 0, HSCX_MASK, 0x0); gazel_interrupt() 269 WriteHSCX(cs, 1, HSCX_MASK, 0x0); gazel_interrupt()
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H A D | diva.c | 309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); diva_interrupt() 310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); diva_interrupt() 313 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); diva_interrupt() 314 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0); diva_interrupt()
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H A D | sedlbauer.c | 296 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); sedlbauer_interrupt() 297 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); sedlbauer_interrupt() 300 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0x0); sedlbauer_interrupt() 301 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0x0); sedlbauer_interrupt()
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H A D | elsa.c | 333 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF); elsa_interrupt() 334 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF); elsa_interrupt() 355 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0); elsa_interrupt() 356 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0x0); elsa_interrupt()
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