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Searched refs:HIWORD_UPDATE (Results 1 – 7 of 7) sorted by relevance

/linux-4.1.27/drivers/clk/rockchip/
Dclk-pll.c198 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_rate()
202 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_rate()
204 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_rate()
208 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, in rockchip_rk3066_pll_set_rate()
211 writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK, in rockchip_rk3066_pll_set_rate()
216 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_rate()
238 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), in rockchip_rk3066_pll_enable()
248 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, in rockchip_rk3066_pll_disable()
Dclk-cpu.c158 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, in rockchip_cpuclk_pre_rate_change()
160 HIWORD_UPDATE(1, 1, reg_data->mux_core_shift), in rockchip_cpuclk_pre_rate_change()
164 writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift), in rockchip_cpuclk_pre_rate_change()
198 writel(HIWORD_UPDATE(0, reg_data->div_core_mask, in rockchip_cpuclk_post_rate_change()
200 HIWORD_UPDATE(0, 1, reg_data->mux_core_shift), in rockchip_cpuclk_post_rate_change()
Dclk-rk3188.c118 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
124 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
126 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
128 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
130 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
166 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
Dclk-rk3288.c121 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
123 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
129 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
131 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
133 HIWORD_UPDATE(_pclk_dbg_pre, \
Dclk-mmc-phase.c105 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg); in rockchip_mmc_set_phase()
Dclk.h30 #define HIWORD_UPDATE(val, mask, shift) \ macro
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-rk.c55 #define HIWORD_UPDATE(val, mask, shift) \ macro
87 #define GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
88 #define GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)