Searched refs:GxICR (Results 1 - 16 of 16) sorted by relevance

/linux-4.1.27/arch/mn10300/kernel/
H A Dirq.c48 tmp = GxICR(irq); mn10300_cpupic_ack()
59 tmp = GxICR(irq); __mask_and_set_icr()
60 GxICR(irq) = (tmp & mask) | set; __mask_and_set_icr()
61 tmp = GxICR(irq); __mask_and_set_icr()
80 tmp = GxICR(irq); mn10300_cpupic_mask_ack()
81 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; mn10300_cpupic_mask_ack()
82 tmp = GxICR(irq); mn10300_cpupic_mask_ack()
85 tmp = GxICR(irq); mn10300_cpupic_mask_ack()
86 GxICR(irq) = (tmp & GxICR_LEVEL); mn10300_cpupic_mask_ack()
87 tmp2 = GxICR(irq); mn10300_cpupic_mask_ack()
121 tmp = GxICR(irq); mn10300_cpupic_unmask_clear()
122 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; mn10300_cpupic_unmask_clear()
123 tmp = GxICR(irq); mn10300_cpupic_unmask_clear()
125 tmp = GxICR(irq); mn10300_cpupic_unmask_clear()
334 x = GxICR(irq); migrate_irqs()
335 GxICR(irq) = x & GxICR_LEVEL; migrate_irqs()
336 tmp = GxICR(irq); migrate_irqs()
347 if (GxICR(irq) & GxICR_REQUEST) migrate_irqs()
H A Dsmp-low.S66 movbu d2,(GxICR(FLUSH_CACHE_IPI)) # ACK the interrupt
67 movhu (GxICR(FLUSH_CACHE_IPI)),d2
80 movhu (GxICR(SMP_BOOT_IRQ)),d0
82 movhu d0,(GxICR(SMP_BOOT_IRQ))
H A Dgdb-io-ttysm-low.S57 movbu d2,(GxICR(SCgRXIRQ)) # ACK the interrupt
58 movhu (GxICR(SCgRXIRQ)),d2 # flush
H A Dsmp.c189 GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT; init_ipi()
197 GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; init_ipi()
198 tmp16 = GxICR(CALL_FUNCTION_NMI_IPI); init_ipi()
223 tmp = GxICR(irq); mn10300_ipi_shutdown()
224 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; mn10300_ipi_shutdown()
225 tmp = GxICR(irq); mn10300_ipi_shutdown()
241 tmp = GxICR(irq); mn10300_ipi_enable()
242 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE; mn10300_ipi_enable()
243 tmp = GxICR(irq); mn10300_ipi_enable()
264 tmp = GxICR(irq); mn10300_ipi_disable()
265 GxICR(irq) = tmp & GxICR_LEVEL; mn10300_ipi_disable()
266 tmp = GxICR(irq); mn10300_ipi_disable()
292 tmp = GxICR(irq); mn10300_ipi_ack()
601 GxICR(CALL_FUNC_SINGLE_IPI) = CALL_FUNCTION_GxICR_LV | GxICR_DETECT; smp_cpu_init()
604 GxICR(LOCAL_TIMER_IPI) = LOCAL_TIMER_GxICR_LV | GxICR_DETECT; smp_cpu_init()
607 GxICR(RESCHEDULE_IPI) = RESCHEDULE_GxICR_LV | GxICR_DETECT; smp_cpu_init()
611 GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT; smp_cpu_init()
619 GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; smp_cpu_init()
620 tmp16 = GxICR(CALL_FUNCTION_NMI_IPI); smp_cpu_init()
644 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; smp_prepare_cpu_init()
653 GxICR(DEBUGGER_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; smp_prepare_cpu_init()
654 tmp16 = GxICR(DEBUGGER_NMI_IPI); smp_prepare_cpu_init()
H A Dcevt-mn10300.c79 GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; setup_jiffies_interrupt()
80 tmp = GxICR(irq); setup_jiffies_interrupt()
H A Dmn10300-serial.c47 #undef GxICR macro
48 #define GxICR(X) CROSS_GxICR(X, 0) macro
204 .rx_icr = &GxICR(SC0RXIRQ),
205 .tx_icr = &GxICR(SC0TXIRQ),
266 .rx_icr = &GxICR(SC1RXIRQ),
267 .tx_icr = &GxICR(SC1TXIRQ),
339 .rx_icr = &GxICR(SC2RXIRQ),
340 .tx_icr = &GxICR(SC2TXIRQ),
389 GxICR(irq) = GxICR_LEVEL_6; mn10300_serial_mask_ack()
390 tmp = GxICR(irq); /* flush write buffer */ mn10300_serial_mask_ack()
417 GxICR(d->irq) = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL); mn10300_serial_low_mask()
418 tmp = GxICR(d->irq); /* flush write buffer */ mn10300_serial_low_mask()
428 GxICR(d->irq) = mn10300_serial_low_unmask()
430 tmp = GxICR(d->irq); /* flush write buffer */ mn10300_serial_low_unmask()
H A Dhead.S365 movhu (GxICR(SMP_BOOT_IRQ)),d0
367 movhu d0,(GxICR(SMP_BOOT_IRQ))
368 movhu (GxICR(SMP_BOOT_IRQ)),d0 # flush
H A Dentry.S300 movbu d0,(GxICR(CALL_FUNCTION_NMI_IPI))
301 movhu (GxICR(CALL_FUNCTION_NMI_IPI)),d0
317 movbu d0,(GxICR(DEBUGGER_NMI_IPI))
318 movhu (GxICR(DEBUGGER_NMI_IPI)),d0
/linux-4.1.27/arch/mn10300/include/asm/
H A Dintctl-regs.h22 #define GxICR(X) \ macro
39 #define NMICR GxICR(NMIIRQ) /* NMI control register */
67 #define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
H A Dtimer-regs.h106 #define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */
107 #define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */
108 #define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */
109 #define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */
325 #define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */
326 #define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */
327 #define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */
328 #define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */
329 #define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */
330 #define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */
331 #define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */
333 #define TM12ICR GxICR(TM12IRQ) /* timer 12 uflow intr ctrl reg */
334 #define TM13ICR GxICR(TM13IRQ) /* timer 13 uflow intr ctrl reg */
335 #define TM14ICR GxICR(TM14IRQ) /* timer 14 uflow intr ctrl reg */
336 #define TM15ICR GxICR(TM15IRQ) /* timer 15 uflow intr ctrl reg */
418 #define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */
419 #define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */
420 #define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */
446 #define TMTICR GxICR(TMTIRQ) /* OS Tick timer uflow intr ctrl reg */
447 #define TMSICR GxICR(TMSIRQ) /* Timestamp timer uflow intr ctrl reg */
H A Dserial-regs.h92 #define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
93 #define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
105 #define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
106 #define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
185 #define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
186 #define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
H A Drtc-regs.h70 #define RTICR GxICR(RTIRQ)
/linux-4.1.27/arch/mn10300/proc-mn103e010/include/proc/
H A Ddmactl-regs.h83 #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
84 #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
85 #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
86 #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
/linux-4.1.27/arch/mn10300/proc-mn2ws0050/include/proc/
H A Ddmactl-regs.h84 #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
85 #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
86 #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
87 #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
/linux-4.1.27/arch/mn10300/proc-mn2ws0050/
H A Dproc-init.c76 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; processor_init()
79 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; processor_init()
/linux-4.1.27/arch/mn10300/proc-mn103e010/
H A Dproc-init.c59 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; processor_init()

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