Searched refs:GPLR (Results 1 - 11 of 11) sorted by relevance

/linux-4.1.27/arch/arm/mach-sa1100/
H A Dpm.c59 gpio = GPLR; sa11x0_pm_enter()
H A Dbadge4.c220 !!(GPLR & BADGE4_GPIO_SDTYP1), badge4_init()
221 !!(GPLR & BADGE4_GPIO_SDTYP0)); badge4_init()
240 PGSR |= (GPLR & (BADGE4_GPIO_SDTYP0|BADGE4_GPIO_SDTYP1)); badge4_init()
H A Dassabet.c135 if (GPLR & SDA) adv7171_send()
147 unsigned gplr = GPLR; adv7171_write()
155 if (!(GPLR & SDA)) adv7171_write()
496 unsigned long phys = __PREG(GPLR) & PMD_MASK; map_sa1100_gpio_regs()
527 scr = GPLR; get_assabet_scr()
H A Dh3xxx.c129 * DCD and CTS bits are inverted in GPLR by RS232 transceiver h3xxx_uart_get_mctrl()
H A Djornada720_ssp.c64 while ((GPLR & GPIO_GPIO10)) { jornada_ssp_byte()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.c34 #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5)) macro
362 if (GPLR(i) & GPIO_bit(i)) pxa2xx_mfp_suspend()
373 saved_gplr[i] = GPLR(i * 32); pxa2xx_mfp_suspend()
/linux-4.1.27/drivers/gpio/
H A Dgpio-intel-mid.c54 GPLR = 0, /* pin level read-only */ enumerator in enum:GPIO_REG
67 u32 gplr_offset; /* offset of first GPLR register from base */
121 void __iomem *gplr = gpio_reg(chip, offset, GPLR); intel_gpio_get()
H A Dgpio-sa1100.c20 return GPLR & GPIO_GPIO(offset); sa1100_gpio_get()
H A Dgpio-pxa.c35 * GPLR GPDR GPSR GPCR GRER GFER GEDR
/linux-4.1.27/drivers/input/touchscreen/
H A Djornada720_ts.c75 if (GPLR & GPIO_GPIO(9)) { jornada720_ts_interrupt()
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1117 * GPLR General-Purpose Input/Output (GPIO) Pin Level
1138 #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ macro

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