Searched refs:FRQCRA (Results 1 – 6 of 6) sorted by relevance
| /linux-4.1.27/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7724.c | 31 #define FRQCRA 0xa4150000 macro
88 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; in pll_recalc()
143 value = __raw_readl(FRQCRA); in div4_kick()
145 __raw_writel(value, FRQCRA); in div4_kick()
166 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
167 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
168 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
169 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
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| /linux-4.1.27/arch/sh/include/cpu-sh4/cpu/ |
| D | freq.h | 33 #define FRQCRA 0xa4150000 macro
39 #define FRQCR FRQCRA
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| /linux-4.1.27/arch/sh/boards/mach-se/7724/ |
| D | sdram.S | 62 mov.l FRQCRA,r0
127 FRQCRA: .long 0xa4150000 label
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| /linux-4.1.27/arch/arm/mach-shmobile/ |
| D | clock-r8a7740.c | 42 #define FRQCRA IOMEM(0xe6150000) macro
148 .enable_reg = (void __iomem *)FRQCRA,
318 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
319 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
320 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
321 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
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| D | clock-sh73a0.c | 24 #define FRQCRA IOMEM(0xe6150000) macro
226 [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
232 [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
233 [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
234 [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
235 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
236 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
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| /linux-4.1.27/arch/arm/mach-shmobile/include/mach/ |
| D | head-kzm9g.txt | 92 #define FRQCRA (CPG_BASE + 0x0000)
185 ED FRQCRA, 0x0012453C
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