Searched refs:FPGA_XD_PULL_CTL_EN1 (Results 1 – 2 of 2) sorted by relevance
548 #define FPGA_XD_PULL_CTL_EN1 0xFE macro
510 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20); in reset_xd()540 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | in reset_xd()574 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | in reset_xd()