Searched refs:EXYNOS_DP_SYS_CTL_1 (Results 1 – 2 of 2) sorted by relevance
128 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_reset()1067 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_init_video()1103 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()1104 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()1106 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
47 #define EXYNOS_DP_SYS_CTL_1 0x600 macro