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Searched refs:EXYNOS5_OSCCLK_GATE_SYS_PWR_REG (Results 1 – 2 of 2) sorted by relevance

/linux-4.1.27/arch/arm/mach-exynos/
Dpmu.c378 { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
505 { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
Dregs-pmu.h396 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 macro