Searched refs:EBIU_SDGCTL (Results 1 - 16 of 16) sorted by relevance

/linux-4.1.27/arch/blackfin/mach-common/
H A Dclocks-init.c87 #ifdef EBIU_SDGCTL init_clocks()
103 #ifdef EBIU_SDGCTL init_clocks()
H A Ddpmc_modes.S205 P0.L = lo(EBIU_SDGCTL);
206 P0.H = hi(EBIU_SDGCTL);
237 #elif defined(EBIU_SDGCTL) /* SDRAM */
239 P0.L = lo(EBIU_SDGCTL);
240 P0.H = hi(EBIU_SDGCTL);
/linux-4.1.27/arch/blackfin/include/asm/
H A Dmem_init.h12 #if defined(EBIU_SDGCTL)
/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h474 #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
475 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
H A DdefBF532.h176 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ macro
/linux-4.1.27/arch/blackfin/kernel/
H A Ddebug-mmrs.c891 #ifdef EBIU_SDGCTL bfin_debug_mmrs_init()
898 D32(EBIU_SDGCTL); bfin_debug_mmrs_init()
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h360 #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
361 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
H A DdefBF512.h211 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ macro
965 /* EBIU_SDGCTL Masks */
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h377 #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
378 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
H A DdefBF522.h210 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ macro
966 /* EBIU_SDGCTL Masks */
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
H A DcdefBF561.h485 #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
486 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
H A DdefBF561.h287 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ macro
1305 /* EBIU_SDGCTL Masks */
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF534.h340 #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
341 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
H A DdefBF534.h187 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ macro
1287 /* EBIU_SDGCTL Masks */
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h474 #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
475 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
H A DdefBF538.h182 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ macro
1677 /* EBIU_SDGCTL Masks */

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