Searched refs:DRV_BASE (Results 1 - 1 of 1) sorted by relevance

/linux-4.1.27/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8173.c26 #define DRV_BASE 0xb00 macro
262 MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
263 MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
264 MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
265 MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
266 MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
267 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
268 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
269 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
270 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
271 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
272 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
273 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
274 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
275 MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
276 MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
277 MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
278 MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
287 MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
288 MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
289 MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
290 MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
291 MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
292 MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
293 MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
294 MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
295 MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
296 MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
297 MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
298 MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
299 MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
300 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
313 MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
314 MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
315 MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
316 MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
323 MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
324 MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
325 MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
326 MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
327 MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
328 MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
329 MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
330 MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
331 MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
332 MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
333 MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
334 MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
335 MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
336 MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
337 MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
338 MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
339 MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
340 MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
341 MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
342 MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
343 MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
344 MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
351 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
352 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
353 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
354 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
355 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
356 MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
357 MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
358 MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
359 MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
360 MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
361 MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
362 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
363 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
364 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
365 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
366 MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
367 MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
368 MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
369 MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
370 MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
371 MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
372 MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
373 MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
374 MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
375 MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)

Completed in 58 milliseconds