Searched refs:DMA1_CONFIG (Results 1 - 14 of 14) sorted by relevance

/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h168 #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
169 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
H A DdefBF532.h200 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ macro
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h404 #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
405 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
H A DdefBF512.h237 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ macro
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h421 #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
422 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
H A DdefBF522.h237 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ macro
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF534.h383 #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
384 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
H A DdefBF534.h213 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ macro
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h516 #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
517 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
H A DdefBF538.h214 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ macro
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF54x_base.h342 #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
343 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
H A DdefBF54x_base.h225 #define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */ macro
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
H A DcdefBF60x_base.h368 #define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG)
369 #define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
H A DdefBF60x_base.h1543 #define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */ macro

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