| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_10_DLLoff; in nvkm_gddr3_calc()
88 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
113 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
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| D | sddr3.c | 71 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
82 DLL = !ram->next->bios.ramcfg_10_DLLoff; in nvkm_sddr3_calc()
90 DLL = !(ram->mr[1] & 0x1); in nvkm_sddr3_calc()
114 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
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| D | sddr2.c | 62 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
68 DLL = !ram->next->bios.ramcfg_10_DLLoff; in nvkm_sddr2_calc()
91 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
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| /linux-4.1.27/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 74 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
90 strne r0, [r1] @ rewrite DLLA to force DLL reload
92 strne r0, [r1] @ rewrite DLLB to force DLL reload
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| D | sram243x.S | 66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
186 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
187 bne freq_out @ leave if SDR, no DLL function
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
305 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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| D | sram242x.S | 66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
186 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
187 bne freq_out @ leave if SDR, no DLL function
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
305 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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| D | sram34xx.S | 164 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
172 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
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| /linux-4.1.27/arch/x86/boot/ |
| D | early_serial_console.c | 16 #define DLL 0 /* Divisor Latch Low */ macro
34 outb(divisor & 0xff, port + DLL); in early_serial_init()
104 dll = inb(port + DLL); in probe_baud()
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| /linux-4.1.27/Documentation/sound/oss/ |
| D | mwave | 81 SET MWPATH=C:\MWW\DLL;C:\MWW\MWGAMES;C:\MWW\DSP
84 SET LIBPATH=C:\MWW\DLL
85 SET PATH=C:\WINDOWS;C:\MWW\DLL;
95 SET MWPATH=C:\MWW\DLL;C:\MWW\MWGAMES;C:\MWW\DSP
101 SET LIBPATH=C:\MWW\DLL
102 …DOWS\COMMAND;E:\ORAWIN95\BIN;f:\msdev\bin;e:\v30\bin.dbg;v:\devt\v30\bin;c:\JavaSDK\Bin;C:\MWW\DLL;
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| /linux-4.1.27/Documentation/devicetree/bindings/mmc/ |
| D | fsl-imx-esdhc.txt | 16 This is used to set the clock delay for DLL(Delay Line) on override mode
19 chapter, DLL (Delay Line) section in RM for details.
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| D | sdhci-st.txt | 27 to configure DLL inside the flashSS, if so reg-names must also be
32 for eMMC on stih407 family silicon to configure DLL inside FlashSS.
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| /linux-4.1.27/arch/frv/kernel/ |
| D | debug-stub.c | 220 __UART0(DLL) = value & 0xff; in console_set_baud()
241 value |= __UART0(DLL); in console_get_baud()
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| D | gdb-io.c | 100 __UART(DLL) = value & 0xff; in gdbstub_set_baud()
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| /linux-4.1.27/arch/arm/mach-orion5x/ |
| D | tsx09-common.c | 37 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
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| D | terastation_pro2-setup.c | 280 writel(divisor & 0xff, UART1_REG(DLL)); in tsp2_power_off()
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| D | kurobox_pro-setup.c | 301 writel(divisor & 0xff, UART1_REG(DLL)); in kurobox_pro_power_off()
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| /linux-4.1.27/drivers/usb/serial/ |
| D | io_16654.h | 43 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB macro
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| D | mos7720.c | 134 DLL, enumerator
1380 write_mos_reg(serial, port_number, DLL, 0x01); in set_higher_rates()
1494 write_mos_reg(serial, number, DLL, (__u8)(divisor & 0xff)); in send_cmd_write_baud_rate()
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| D | io_edgeport.c | 2269 MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, DLL, LOW8(divisor)); in send_cmd_write_baud_rate()
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| /linux-4.1.27/arch/x86/kernel/ |
| D | early_printk.c | 95 #define DLL 0 /* Divisor Latch Low */ macro
142 serial_out(early_serial_base, DLL, divisor & 0xff); in early_serial_hw_init()
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| /linux-4.1.27/drivers/power/reset/ |
| D | qnap-poweroff.c | 66 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_power_off()
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| /linux-4.1.27/drivers/net/hamradio/ |
| D | baycom_ser_fdx.c | 116 #define DLL(iobase) (iobase+0) macro
188 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
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| D | baycom_ser_hdx.c | 104 #define DLL(iobase) (iobase+0) macro
175 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
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| D | yam.c | 174 #define DLL(iobase) (iobase+0) macro
310 outb(1, DLL(iobase)); in fpga_reset()
482 outb(divisor, DLL(dev->base_addr)); in yam_set_uart()
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| /linux-4.1.27/arch/arm/mach-shmobile/include/mach/ |
| D | head-kzm9g.txt | 250 LIST "enable DLL oscillation in DDRPHY"
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| /linux-4.1.27/arch/blackfin/kernel/ |
| D | debug-mmrs.c | 547 __UART(DLL, dll); in bfin_debug_mmrs_uart()
560 __UART(DLL, dll); in bfin_debug_mmrs_uart()
|