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Searched refs:DISPLAY_PLANE_ENABLE (Results 1 – 11 of 11) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/gma500/
Dmdfld_intel_display.c253 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_disable_crtc()
255 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_disable_crtc()
365 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in mdfld_crtc_dpms()
367 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
393 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
409 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
441 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_crtc_dpms()
443 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
863 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; in mdfld_crtc_mode_set()
Doaktrail_hdmi.c358 dspcntr |= DISPLAY_PLANE_ENABLE; in oaktrail_crtc_hdmi_mode_set()
392 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
393 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
460 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
461 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
Doaktrail_crtc.c277 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_dpms()
279 temp | DISPLAY_PLANE_ENABLE, in oaktrail_crtc_dpms()
303 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_dpms()
305 temp & ~DISPLAY_PLANE_ENABLE, i); in oaktrail_crtc_dpms()
Dgma_display.c244 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in gma_crtc_dpms()
246 temp | DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
291 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in gma_crtc_dpms()
293 temp & ~DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
Dmdfld_device.c357 PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); in mdfld_restore_display_registers()
Dpsb_intel_display.c212 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()
Dpsb_intel_reg.h636 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
Dcdv_intel_display.c733 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_sprite.c174 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); in intel_update_primary_plane()
176 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); in intel_update_primary_plane()
Dintel_display.c1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE); in assert_plane()
1350 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, in assert_planes_disabled()
1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, in assert_planes_disabled()
2697 dspcntr |= DISPLAY_PLANE_ENABLE; in i9xx_update_primary_plane()
2823 dspcntr |= DISPLAY_PLANE_ENABLE; in ironlake_update_primary_plane()
6953 if (!(val & DISPLAY_PLANE_ENABLE)) in i9xx_get_initial_plane_config()
8114 if (!(val & DISPLAY_PLANE_ENABLE)) in ironlake_get_initial_plane_config()
13924 if ((val & DISPLAY_PLANE_ENABLE) && in intel_check_plane_mapping()
14127 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
Di915_reg.h4468 #define DISPLAY_PLANE_ENABLE (1<<31) macro