Searched refs:CPG_PLL0CR (Results 1 – 3 of 3) sorted by relevance
30 #define CPG_PLL0CR 0xd8 macro98 u32 value = clk_readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
32 #define CPG_PLL0CR 0xd8 macro99 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
32 #define CPG_PLL0CR 0x000000d8 macro320 u32 value = clk_readl(cpg->reg + CPG_PLL0CR); in rcar_gen2_cpg_register_clock()