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Searched refs:CLOCK_CNTL_INDEX (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/drivers/video/fbdev/aty/
Dradeonfb.h445 save = INREG(CLOCK_CNTL_INDEX); in radeon_pll_errata_after_data()
447 OUTREG(CLOCK_CNTL_INDEX, tmp); in radeon_pll_errata_after_data()
449 OUTREG(CLOCK_CNTL_INDEX, save); in radeon_pll_errata_after_data()
457 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); in __INPLL()
468 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); in __OUTPLL()
Dradeon_accel.c200 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); in radeonfb_engine_reset()
253 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); in radeonfb_engine_reset()
Dradeon_pm.c1481 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1516 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1637 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1655 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1682 OUTREG8(CLOCK_CNTL_INDEX+1, 0); in radeon_pm_restore_pixel_pll()
2276 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2299 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2429 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2453 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2458 tmp = INREG(CLOCK_CNTL_INDEX);
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Daty128fb.c585 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); in _aty_ld_pll()
593 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); in _aty_st_pll()
719 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); in aty128_reset_engine()
731 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); in aty128_reset_engine()
1349 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); in aty128_set_pll()
Dradeon_base.c528 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_probe_pll_params()
1231 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; in radeon_save_state()
1259 OUTREGP(CLOCK_CNTL_INDEX, in radeon_write_pll_regs()
1277 OUTREGP(CLOCK_CNTL_INDEX, in radeon_write_pll_regs()
Dradeon_monitor.c665 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_fixup_panel_info()
/linux-4.1.27/include/video/
Daty128.h12 #define CLOCK_CNTL_INDEX 0x0008 macro
Dradeon.h306 #define CLOCK_CNTL_INDEX 0x0008 macro