Searched refs:CLK_SOURCE_CSITE (Results 1 – 4 of 4) sorted by relevance
107 #define CLK_SOURCE_CSITE 0x1d4 macro961 readl(clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()962 writel(3<<30, clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()1011 clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_resume()
144 #define CLK_SOURCE_CSITE 0x1d4 macro1247 readl(clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_suspend()1248 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_suspend()1259 clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_resume()
39 #define CLK_SOURCE_CSITE 0x1d4 macro1332 readl(clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_suspend()1333 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_suspend()1339 clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_resume()
63 #define CLK_SOURCE_CSITE 0x1d4 macro496 …MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_c…