Searched refs:CLK_SCLK_AUD_CA5 (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h812 #define CLK_SCLK_AUD_CA5 40 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h812 #define CLK_SCLK_AUD_CA5 40 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h812 #define CLK_SCLK_AUD_CA5 40 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h812 #define CLK_SCLK_AUD_CA5 40 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h812 #define CLK_SCLK_AUD_CA5 40 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dexynos5433.h812 #define CLK_SCLK_AUD_CA5 40 macro
/linux-4.1.27/drivers/clk/samsung/
H A Dclk-exynos5433.c3030 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,

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