Searched refs:CLK_RESET_PLLX_BASE (Results 1 – 2 of 2) sorted by relevance
| /linux-4.1.27/arch/arm/mach-tegra/ |
| D | sleep-tegra30.S | 68 #define CLK_RESET_PLLX_BASE 0xe0 macro
357 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
370 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
380 pll_locked r1, r0, CLK_RESET_PLLX_BASE
650 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
652 str r0, [r5, #CLK_RESET_PLLX_BASE]
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| /linux-4.1.27/drivers/clk/tegra/ |
| D | clk-tegra30.c | 148 #define CLK_RESET_PLLX_BASE 0xe0 macro
1277 readl(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_suspend()
1304 clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()
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