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Searched refs:CLK_CTL (Results 1 – 6 of 6) sorted by relevance

/linux-4.1.27/drivers/mmc/host/
Drtsx_pci_sdmmc.c630 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); in sd_change_phase()
640 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); in sd_change_phase()
991 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
995 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1003 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1023 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
/linux-4.1.27/drivers/staging/rts5208/
Drtsx_card.c681 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in switch_ssc_clock()
701 retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0); in switch_ssc_clock()
799 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); in switch_normal_clock()
846 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0); in switch_normal_clock()
Drtsx_card.h831 #define CLK_CTL 0xFC02 macro
Dsd.c927 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, in sd_change_phase()
951 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0); in sd_change_phase()
978 retval = rtsx_write_register(chip, CLK_CTL, in sd_change_phase()
1030 retval = rtsx_write_register(chip, CLK_CTL, in sd_change_phase()
/linux-4.1.27/drivers/mfd/
Drtsx_pcr.c713 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rtsx_pci_switch_clock()
735 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rtsx_pci_switch_clock()
/linux-4.1.27/include/linux/mfd/
Drtsx_pci.h459 #define CLK_CTL 0xFC02 macro