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Searched refs:CLKDEV_CON_ID (Results 1 – 22 of 22) sorted by relevance

/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
Dclock-sh7366.c197 CLKDEV_CON_ID("rclk", &r_clk),
198 CLKDEV_CON_ID("extal", &extal_clk),
199 CLKDEV_CON_ID("dll_clk", &dll_clk),
200 CLKDEV_CON_ID("pll_clk", &pll_clk),
203 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
204 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
205 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
206 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
207 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
208 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
Dclock-sh7343.c199 CLKDEV_CON_ID("rclk", &r_clk),
200 CLKDEV_CON_ID("extal", &extal_clk),
201 CLKDEV_CON_ID("dll_clk", &dll_clk),
202 CLKDEV_CON_ID("pll_clk", &pll_clk),
205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
209 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
210 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
Dclock-sh7734.c183 CLKDEV_CON_ID("extal", &extal_clk),
184 CLKDEV_CON_ID("pll_clk", &pll_clk),
187 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
188 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
189 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]),
190 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
191 CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]),
192 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
203 CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]),
207 CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]),
[all …]
Dclock-sh7723.c208 CLKDEV_CON_ID("rclk", &r_clk),
209 CLKDEV_CON_ID("extal", &extal_clk),
210 CLKDEV_CON_ID("dll_clk", &dll_clk),
211 CLKDEV_CON_ID("pll_clk", &pll_clk),
214 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
215 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
216 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
217 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
218 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
219 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
Dclock-sh7786.c130 CLKDEV_CON_ID("extal", &extal_clk),
131 CLKDEV_CON_ID("pll_clk", &pll_clk),
134 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
135 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
136 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
137 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
138 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
139 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
149 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
150 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
[all …]
Dclock-sh7785.c121 CLKDEV_CON_ID("extal", &extal_clk),
122 CLKDEV_CON_ID("pll_clk", &pll_clk),
125 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
126 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
127 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
128 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
129 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
130 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
131 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
132 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
[all …]
Dclock-sh7724.c273 CLKDEV_CON_ID("rclk", &r_clk),
274 CLKDEV_CON_ID("extal", &extal_clk),
275 CLKDEV_CON_ID("fll_clk", &fll_clk),
276 CLKDEV_CON_ID("pll_clk", &pll_clk),
277 CLKDEV_CON_ID("div3_clk", &div3_clk),
280 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
281 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
282 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
283 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
284 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
[all …]
Dclock-sh7722.c183 CLKDEV_CON_ID("rclk", &r_clk),
184 CLKDEV_CON_ID("extal", &extal_clk),
185 CLKDEV_CON_ID("dll_clk", &dll_clk),
186 CLKDEV_CON_ID("pll_clk", &pll_clk),
189 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
190 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
191 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
192 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
193 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
194 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
Dclock-sh7757.c107 CLKDEV_CON_ID("extal", &extal_clk),
108 CLKDEV_CON_ID("pll_clk", &pll_clk),
111 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
112 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
113 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
117 CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]),
118 CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]),
119 CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]),
120 CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]),
121 CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]),
[all …]
Dclock-shx3.c105 CLKDEV_CON_ID("extal", &extal_clk),
106 CLKDEV_CON_ID("pll_clk", &pll_clk),
109 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
110 CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
111 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
112 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
113 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
114 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
122 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
123 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
[all …]
Dclock-sh7763.c96 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
Dclock-sh7780.c102 CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c109 CLKDEV_CON_ID("rclk", &r_clk),
110 CLKDEV_CON_ID("extal", &extal_clk),
111 CLKDEV_CON_ID("pll_clk", &pll_clk),
114 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
115 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
118 CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
119 CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
121 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
123 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
124 CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
[all …]
Dclock-sh7269.c143 CLKDEV_CON_ID("rclk", &r_clk),
144 CLKDEV_CON_ID("extal", &extal_clk),
145 CLKDEV_CON_ID("pll_clk", &pll_clk),
146 CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
149 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
150 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
162 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
164 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
165 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
/linux-4.1.27/arch/arm/mach-shmobile/
Dclock-r8a7740.c510 CLKDEV_CON_ID("extalr", &extalr_clk),
511 CLKDEV_CON_ID("extal1", &extal1_clk),
512 CLKDEV_CON_ID("extal2", &extal2_clk),
513 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
514 CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
515 CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
516 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
517 CLKDEV_CON_ID("dv_clk", &dv_clk),
518 CLKDEV_CON_ID("system_clk", &system_clk),
519 CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
[all …]
Dclock-r8a7779.c147 CLKDEV_CON_ID("plla_clk", &plla_clk),
148 CLKDEV_CON_ID("clkz_clk", &clkz_clk),
149 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
152 CLKDEV_CON_ID("shyway_clk", &clks_clk),
153 CLKDEV_CON_ID("bus_clk", &clkout_clk),
154 CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
155 CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
156 CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
157 CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
Dclock-sh73a0.c613 CLKDEV_CON_ID("r_clk", &r_clk),
620 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
621 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
622 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
623 CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
624 CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
625 CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
Dclock-r8a7778.c174 CLKDEV_CON_ID("shyway_clk", &s_clk),
175 CLKDEV_CON_ID("peripheral_clk", &p_clk),
/linux-4.1.27/arch/sh/kernel/cpu/
Dclock-cpg.c40 CLKDEV_CON_ID("master_clk", &master_clk),
41 CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
42 CLKDEV_CON_ID("bus_clk", &bus_clk),
43 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
/linux-4.1.27/arch/sh/kernel/cpu/sh4/
Dclock-sh4-202.c152 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
153 CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk),
154 CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
/linux-4.1.27/include/linux/
Dsh_clk.h203 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro
/linux-4.1.27/arch/sh/boards/mach-highlander/
Dsetup.c340 CLKDEV_CON_ID("ivdr_clk", &ivdr_clk),