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Searched refs:CG_SPLL_FUNC_CNTL_2 (Results 1 – 15 of 15) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Drv740d.h34 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
Drv730d.h37 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
Drv770.c1139 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_set_clk_bypass_mode()
1142 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
1151 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
Drv740_dpm.c292 RREG32(CG_SPLL_FUNC_CNTL_2); in rv740_read_clock_registers()
Drv730_dpm.c205 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
Drv770d.h100 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
Dnid.h540 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
Dsid.h94 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
Dcikd.h259 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 macro
Dsi.c3989 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3991 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
3999 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4001 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
Devergreend.h82 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
Drv770_dpm.c1524 RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_read_clock_registers()
Dni_dpm.c1184 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in ni_read_clock_registers()
Dsi_dpm.c3511 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
Dci_dpm.c1847 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); in ci_read_clock_registers()