Searched refs:CG_SPLL_FUNC_CNTL (Results 1 – 18 of 18) sorted by relevance
26 #define CG_SPLL_FUNC_CNTL 0x600 macro
211 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()986 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()1008 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
290 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
319 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()321 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()329 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
203 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
89 #define CG_SPLL_FUNC_CNTL 0x600 macro
3985 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()3987 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()4016 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()4018 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()4020 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()4022 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
531 #define CG_SPLL_FUNC_CNTL 0x600 macro
85 #define CG_SPLL_FUNC_CNTL 0x600 macro
250 #define CG_SPLL_FUNC_CNTL 0xC0500140 macro
74 #define CG_SPLL_FUNC_CNTL 0x600 macro
1270 #define CG_SPLL_FUNC_CNTL 0x600 macro
1522 RREG32(CG_SPLL_FUNC_CNTL); in rv770_read_clock_registers()
1183 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in ni_read_clock_registers()
3510 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
1845 RREG32_SMC(CG_SPLL_FUNC_CNTL); in ci_read_clock_registers()