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Searched refs:CGU0_DIV (Results 1 – 4 of 4) sorted by relevance

/linux-4.1.27/arch/blackfin/mach-bf609/
Dclock.c190 u32 div = bfin_read32(CGU0_DIV); in sys_clk_get_rate()
238 u32 div = bfin_read32(CGU0_DIV); in sys_clk_set_rate()
250 clk_reg_write_mask(CGU0_DIV, div << clk->shift, in sys_clk_set_rate()
/linux-4.1.27/arch/blackfin/include/asm/
Dmem_init.h454 bfin_write32(CGU0_DIV, cgu_div); in init_cgu()
461 bfin_write32(CGU0_DIV, cgu_div | UPDT); in init_cgu()
/linux-4.1.27/drivers/cpufreq/
Dblackfin-cpufreq.c77 csel = bfin_read32(CGU0_DIV) & 0x1F; in bfin_init_tables()
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h3207 #define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */ macro