Searched refs:CCR2 (Results 1 – 6 of 6) sorted by relevance
| /linux-4.1.27/drivers/net/wan/ |
| D | dscc4.c | 271 #define CCR2 0x10 macro
629 scc_writel(0x00050000, dpriv, dev, CCR2);
870 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2); in dscc4_init_registers()
1072 scc_patchl(0, 0x00050000, dpriv, dev, CCR2); in dscc4_open()
1192 scc_patchl(0x00050000, 0, dpriv, dev, CCR2); in dscc4_close()
1672 scc_writel(0x08050008, dpriv, dev, CCR2); in dscc4_tx_irq()
1810 scc_patchl(RxActivate, 0, dpriv, dev, CCR2); in dscc4_rx_irq()
1863 scc_patchl(0, RxActivate, dpriv, dev, CCR2); in dscc4_rx_irq()
|
| /linux-4.1.27/include/linux/ |
| D | omap-dma.h | 152 CPC, CCR2, LCH_CTRL, enumerator
|
| /linux-4.1.27/arch/arm/mach-omap1/ |
| D | dma.c | 78 [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
|
| /linux-4.1.27/drivers/char/pcmcia/ |
| D | synclink_cs.c | 270 #define CCR2 0x2e macro
2932 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; in mgslpc_set_rate()
2934 write_reg(info, (unsigned char) (channel + CCR2), val); in mgslpc_set_rate()
3001 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
3003 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
3036 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3037 write_reg(info, CHA + CCR2, val); in loopback_enable()
3170 write_reg(info, CHA + CCR2, val); in hdlc_mode()
3487 write_reg(info, CHA + CCR2, 0x10); in async_mode()
|
| /linux-4.1.27/arch/arm/plat-omap/ |
| D | dma.c | 238 ccr = p->dma_read(CCR2, lch); in omap_set_dma_transfer_params()
242 p->dma_write(ccr, CCR2, lch); in omap_set_dma_transfer_params()
|
| /linux-4.1.27/drivers/dma/ |
| D | omap-dma.c | 409 omap_dma_chan_write(c, CCR2, d->ccr >> 16); in omap_dma_start_desc()
|