Searched refs:CACHE_MODE_0_GEN7 (Results 1 – 3 of 3) sorted by relevance
6153 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in haswell_init_clock_gating()6156 I915_WRITE(CACHE_MODE_0_GEN7, in haswell_init_clock_gating()6212 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ivybridge_init_clock_gating()6256 I915_WRITE(CACHE_MODE_0_GEN7, in ivybridge_init_clock_gating()6319 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in valleyview_init_clock_gating()
840 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); in bdw_init_workarounds()885 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); in chv_init_workarounds()
1520 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ macro