Searched refs:C400_CONTROL_STATUS_REG (Results 1 – 3 of 3) sorted by relevance
531 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE | CSR_TRANS_DIR); in NCR5380_pread()537 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pread()541 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY); in NCR5380_pread()558 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()577 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) in NCR5380_pread()585 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) in NCR5380_pread()616 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE); in NCR5380_pwrite()619 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pwrite()627 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()642 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()[all …]
161 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */ macro
848 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE); in NCR5380_init()