Searched refs:BEGIN_RING (Results 1 - 9 of 9) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/r128/
H A Dr128_state.c46 BEGIN_RING((count < 3 ? count : 3) * 5 + 2); r128_emit_clip_rects()
89 BEGIN_RING(2); r128_emit_core()
104 BEGIN_RING(13); r128_emit_context()
130 BEGIN_RING(3); r128_emit_setup()
146 BEGIN_RING(5); r128_emit_masks()
165 BEGIN_RING(2); r128_emit_window()
182 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); r128_emit_tex0()
207 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); r128_emit_tex1()
302 BEGIN_RING(6); r128_clear_box()
384 BEGIN_RING(2); r128_cce_dispatch_clear()
393 BEGIN_RING(6); r128_cce_dispatch_clear()
414 BEGIN_RING(6); r128_cce_dispatch_clear()
435 BEGIN_RING(6); r128_cce_dispatch_clear()
479 BEGIN_RING(7); r128_cce_dispatch_swap()
515 BEGIN_RING(2); r128_cce_dispatch_swap()
536 BEGIN_RING(4); r128_cce_dispatch_flip()
556 BEGIN_RING(2); r128_cce_dispatch_flip()
595 BEGIN_RING(5); r128_cce_dispatch_vertex()
614 BEGIN_RING(2); r128_cce_dispatch_vertex()
659 BEGIN_RING(3); r128_cce_dispatch_indirect()
672 BEGIN_RING(2); r128_cce_dispatch_indirect()
753 BEGIN_RING(2); r128_cce_dispatch_indices()
813 BEGIN_RING(2); r128_cce_dispatch_blit()
866 BEGIN_RING(2); r128_cce_dispatch_blit()
918 BEGIN_RING(6); r128_cce_dispatch_write_span()
942 BEGIN_RING(6); r128_cce_dispatch_write_span()
1024 BEGIN_RING(6); r128_cce_dispatch_write_pixels()
1048 BEGIN_RING(6); r128_cce_dispatch_write_pixels()
1093 BEGIN_RING(7); r128_cce_dispatch_read_span()
1155 BEGIN_RING(7); r128_cce_dispatch_read_pixels()
1194 BEGIN_RING(33); r128_cce_dispatch_stipple()
1570 BEGIN_RING(2); r128_cce_indirect()
H A Dr128_drv.h479 #define BEGIN_RING(n) do { \ macro
481 DRM_INFO("BEGIN_RING(%d)\n", (n)); \
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dr300_cmdbuf.c74 BEGIN_RING(6 + nr * 2); r300_emit_cliprects()
141 BEGIN_RING(2); r300_emit_cliprects()
147 BEGIN_RING(2); r300_emit_cliprects()
151 BEGIN_RING(2); r300_emit_cliprects()
335 BEGIN_RING(1 + sz); r300_emit_carefully_checked_packet0()
379 BEGIN_RING(1 + sz); r300_emit_packet0()
410 BEGIN_RING(6); r300_emit_vpu()
421 BEGIN_RING(3 + sz * 4); r300_emit_vpu()
427 BEGIN_RING(2); r300_emit_vpu()
447 BEGIN_RING(10); r300_emit_clear()
454 BEGIN_RING(4); r300_emit_clear()
525 BEGIN_RING(count + 2); r300_emit_3d_load_vbpntr()
571 BEGIN_RING(count+2); r300_emit_bitblt_multi()
599 BEGIN_RING(count+2); r300_emit_draw_indx_2()
644 BEGIN_RING(4); r300_emit_draw_indx_2()
717 BEGIN_RING(count + 2); r300_emit_raw_packet3()
811 BEGIN_RING(2); r300_pacify()
816 BEGIN_RING(2); r300_pacify()
821 BEGIN_RING(2); r300_pacify()
826 BEGIN_RING(2); r300_pacify()
830 BEGIN_RING(2); r300_pacify()
835 BEGIN_RING(4); r300_pacify()
896 BEGIN_RING(2); r300_cmd_wait()
954 BEGIN_RING(2); r300_scratch()
996 BEGIN_RING(3 + sz * stride); r300_emit_r500fp()
1097 BEGIN_RING(header->delay.count); r300_do_cp_cmdbuf()
1178 BEGIN_RING(2); r300_do_cp_cmdbuf()
H A Dr600_blit.c94 BEGIN_RING(21 + 2); set_render_target()
101 BEGIN_RING(21); set_render_target()
147 BEGIN_RING(5); cp_set_surface_sync()
183 BEGIN_RING(9 + 12); set_shaders()
231 BEGIN_RING(9); set_vtx_resource()
279 BEGIN_RING(9); set_tex_resource()
299 BEGIN_RING(12); set_scissors()
323 BEGIN_RING(10); draw_auto()
502 BEGIN_RING(r7xx_default_size + 10); set_default_state()
506 BEGIN_RING(r6xx_default_size + 10); set_default_state()
577 BEGIN_RING(5); r600_done_blit_copy()
H A Dradeon_state.c184 BEGIN_RING(2); radeon_check_and_fixup_packets()
457 BEGIN_RING(4); radeon_emit_clip_rect()
489 BEGIN_RING(14); radeon_emit_state()
508 BEGIN_RING(2); radeon_emit_state()
515 BEGIN_RING(5); radeon_emit_state()
525 BEGIN_RING(5); radeon_emit_state()
535 BEGIN_RING(4); radeon_emit_state()
544 BEGIN_RING(7); radeon_emit_state()
556 BEGIN_RING(4); radeon_emit_state()
565 BEGIN_RING(2); radeon_emit_state()
578 BEGIN_RING(9); radeon_emit_state()
598 BEGIN_RING(9); radeon_emit_state()
618 BEGIN_RING(9); radeon_emit_state()
643 BEGIN_RING(3); radeon_emit_state2()
788 BEGIN_RING(4); radeon_clear_box()
794 BEGIN_RING(6); radeon_clear_box()
911 BEGIN_RING(4); radeon_cp_dispatch_clear()
937 BEGIN_RING(6); radeon_cp_dispatch_clear()
959 BEGIN_RING(6); radeon_cp_dispatch_clear()
1035 BEGIN_RING(8); radeon_cp_dispatch_clear()
1067 BEGIN_RING(4); radeon_cp_dispatch_clear()
1090 BEGIN_RING(4); radeon_cp_dispatch_clear()
1118 BEGIN_RING(4); radeon_cp_dispatch_clear()
1141 BEGIN_RING(4); radeon_cp_dispatch_clear()
1229 BEGIN_RING(26); radeon_cp_dispatch_clear()
1258 BEGIN_RING(14); radeon_cp_dispatch_clear()
1305 BEGIN_RING(13); radeon_cp_dispatch_clear()
1329 BEGIN_RING(15); radeon_cp_dispatch_clear()
1365 BEGIN_RING(4); radeon_cp_dispatch_clear()
1392 BEGIN_RING(2); radeon_cp_dispatch_swap()
1406 BEGIN_RING(9); radeon_cp_dispatch_swap()
1443 BEGIN_RING(4); radeon_cp_dispatch_swap()
1471 BEGIN_RING(6); radeon_cp_dispatch_flip()
1491 BEGIN_RING(2); radeon_cp_dispatch_flip()
1561 BEGIN_RING(5); radeon_cp_dispatch_vertex()
1589 BEGIN_RING(3); radeon_cp_discard_buffer()
1593 BEGIN_RING(2); radeon_cp_discard_buffer()
1626 BEGIN_RING(3); radeon_cp_dispatch_indirect()
1724 BEGIN_RING(4); radeon_cp_dispatch_texture()
1899 BEGIN_RING(9); radeon_cp_dispatch_texture()
1930 BEGIN_RING(4); radeon_cp_dispatch_texture()
1946 BEGIN_RING(35); radeon_cp_dispatch_stipple()
2191 BEGIN_RING(6); radeon_do_init_pageflip()
2527 BEGIN_RING(2); radeon_cp_indirect()
2662 BEGIN_RING(sz + 1); radeon_emit_packets()
2679 BEGIN_RING(3 + sz); radeon_emit_scalars()
2699 BEGIN_RING(3 + sz); radeon_emit_scalars2()
2717 BEGIN_RING(5 + sz); radeon_emit_vectors()
2741 BEGIN_RING(5 + sz); radeon_emit_veclinear()
2769 BEGIN_RING(cmdsz); radeon_emit_packet3()
2817 BEGIN_RING(2); radeon_emit_packet3_cliprect()
2824 BEGIN_RING(cmdsz); radeon_emit_packet3_cliprect()
2846 BEGIN_RING(2); radeon_emit_wait()
2851 BEGIN_RING(2); radeon_emit_wait()
2856 BEGIN_RING(2); radeon_emit_wait()
H A Dradeon_irq.c232 BEGIN_RING(4); radeon_emit_irq()
H A Dr600_cp.c2312 BEGIN_RING(5); r600_do_cp_idle()
2334 BEGIN_RING(7); r600_do_cp_start()
2406 BEGIN_RING(4); r600_cp_dispatch_indirect()
2472 BEGIN_RING(3); r600_cp_dispatch_swap()
2577 BEGIN_RING(3); r600_cs_id_emit()
H A Dradeon_cp.c589 BEGIN_RING(6); radeon_do_cp_idle()
618 BEGIN_RING(3); radeon_do_cp_start()
626 BEGIN_RING(8); radeon_do_cp_start()
668 BEGIN_RING(2); radeon_do_cp_stop()
2001 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ radeon_wait_ring()
H A Dradeon_drv.h2067 #define BEGIN_RING( n ) do { \ macro
2069 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \

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