Searched refs:AVIVO_D1CRTC_CONTROL (Results 1 - 5 of 5) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
H A Drv515.c308 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; rv515_mc_stop()
311 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); rv515_mc_stop()
316 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); rv515_mc_stop()
329 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); rv515_mc_stop()
331 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); rv515_mc_stop()
450 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); rv515_mc_resume()
452 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); rv515_mc_resume()
H A Drs600.c92 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) avivo_wait_for_vblank()
320 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); rs600_pm_prepare()
322 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); rs600_pm_prepare()
338 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); rs600_pm_finish()
340 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); rs600_pm_finish()
H A Dr500_reg.h348 #define AVIVO_D1CRTC_CONTROL 0x6080 macro
H A Dradeon_device.c670 reg = RREG32(AVIVO_D1CRTC_CONTROL) | radeon_card_posted()
H A Dr600.c1539 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { r600_is_display_hung()

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