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Searched refs:AR_PHY_AGC_CONTROL (Results 1 – 5 of 5) sorted by relevance

/linux-4.1.27/drivers/net/wireless/ath/ath9k/
Dcalib.c224 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
228 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
231 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
234 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
270 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
272 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
274 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
284 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & in ath9k_hw_loadnf()
302 REG_READ(ah, AR_PHY_AGC_CONTROL)); in ath9k_hw_loadnf()
369 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ath9k_hw_getnf()
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Dar9003_calib.c350 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
354 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
355 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
357 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
371 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
375 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
377 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
391 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
392 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
394 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
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Dar9002_calib.c666 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF); in ar9002_hw_calibrate()
723 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
726 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
727 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
739 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
741 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
742 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, in ar9285_hw_cl_cal()
752 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
828 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
833 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
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Dar9003_phy.c316 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
334 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
Dreg.h2038 #define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AG… macro