Home
last modified time | relevance | path

Searched refs:APMU_SDH1 (Results 1 – 7 of 7) sorted by relevance

/linux-4.1.27/drivers/clk/mmp/
Dclk-of-pxa168.c43 #define APMU_SDH1 0x58 macro
183 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
199 …{PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh…
Dclk-of-pxa910.c41 #define APMU_SDH1 0x58 macro
185 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
201 …{PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh…
Dclk-pxa910.c39 #define APMU_SDH1 0x58 macro
276 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); in pxa910_clk_init()
280 apmu_base + APMU_SDH1, 0x1b, &clk_lock); in pxa910_clk_init()
Dclk-pxa168.c41 #define APMU_SDH1 0x58 macro
301 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); in pxa168_clk_init()
304 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, in pxa168_clk_init()
Dclk-of-mmp2.c47 #define APMU_SDH1 0x58 macro
225 …{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sd…
Dclk-mmp2.c45 #define APMU_SDH1 0x58 macro
349 clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, in mmp2_clk_init()
/linux-4.1.27/arch/arm/mach-mmp/
Dclock-mmp2.c43 #define APMU_SDH1 APMU_REG(0x058) macro