| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 46 #define APMU_CCIC0 0x50 macro
185 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
186 …_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0…
190 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
201 …{PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
202 …{PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x…
203 …{PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300…
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| D | clk-of-pxa910.c | 44 #define APMU_CCIC0 0x50 macro
187 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
188 …_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0…
192 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
203 …{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
204 …{PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x…
205 …{PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300…
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| D | clk-pxa910.c | 42 #define APMU_CCIC0 0x50 macro
304 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa910_clk_init()
308 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa910_clk_init()
314 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa910_clk_init()
318 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa910_clk_init()
322 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in pxa910_clk_init()
327 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa910_clk_init()
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| D | clk-of-mmp2.c | 53 #define APMU_CCIC0 0x50 macro
217 {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
231 …{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800,…
232 …{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0…
233 …{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24…
234 …{MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, …
251 ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0; in mmp2_axi_periph_clk_init()
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| D | clk-pxa168.c | 44 #define APMU_CCIC0 0x50 macro
333 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
337 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa168_clk_init()
343 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa168_clk_init()
347 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa168_clk_init()
351 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in pxa168_clk_init()
356 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 51 #define APMU_CCIC0 0x50 macro
404 apmu_base + APMU_CCIC0, 0x1800, &clk_lock); in mmp2_clk_init()
410 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
414 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
419 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in mmp2_clk_init()
423 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in mmp2_clk_init()
427 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
432 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in mmp2_clk_init()
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