Searched refs:APBC_PWM3 (Results 1 - 9 of 9) sorted by relevance
| /linux-4.1.27/arch/arm/mach-mmp/ |
| H A D | clock-pxa910.c | 21 #define APBC_PWM3 APBC_REG(0x014) macro
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| H A D | clock-pxa168.c | 21 #define APBC_PWM3 APBC_REG(0x014) macro
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| H A D | clock-mmp2.c | 29 #define APBC_PWM3 APBC_REG(0x048) macro
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| /linux-4.1.27/drivers/clk/mmp/ |
| H A D | clk-of-pxa168.c | 34 #define APBC_PWM3 0x18 macro
144 {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
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| H A D | clk-of-pxa910.c | 34 #define APBC_PWM3 0x18 macro
139 {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
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| H A D | clk-pxa168.c | 32 #define APBC_PWM3 0x18 macro
198 apbc_base + APBC_PWM3, 10, 0, &clk_lock); pxa168_clk_init()
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| H A D | clk-pxa910.c | 32 #define APBC_PWM3 0x18 macro
203 apbc_base + APBC_PWM3, 10, 0, &clk_lock); pxa910_clk_init()
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| H A D | clk-mmp2.c | 39 #define APBC_PWM3 0x48 macro
247 apbc_base + APBC_PWM3, 10, 0, &clk_lock); mmp2_clk_init()
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| H A D | clk-of-mmp2.c | 41 #define APBC_PWM3 0x48 macro
163 {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
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