Searched refs:APBC_PWM1 (Results 1 – 9 of 9) sorted by relevance
| /linux-4.1.27/arch/arm/mach-mmp/ |
| D | clock-pxa910.c | 19 #define APBC_PWM1 APBC_REG(0x00c) macro
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| D | clock-pxa168.c | 19 #define APBC_PWM1 APBC_REG(0x00c) macro
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| D | clock-mmp2.c | 27 #define APBC_PWM1 APBC_REG(0x040) macro
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| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 32 #define APBC_PWM1 0x10 macro
142 …{PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-of-pxa910.c | 32 #define APBC_PWM1 0x10 macro
137 …{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-pxa910.c | 30 #define APBC_PWM1 0x10 macro
195 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa910_clk_init()
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| D | clk-of-mmp2.c | 39 #define APBC_PWM1 0x40 macro
161 …{MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lo…
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| D | clk-pxa168.c | 30 #define APBC_PWM1 0x10 macro
190 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 37 #define APBC_PWM1 0x40 macro
239 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in mmp2_clk_init()
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