Searched refs:APBC_PWM0 (Results 1 – 7 of 7) sorted by relevance
| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 31 #define APBC_PWM0 0xc macro
141 …{PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-of-pxa910.c | 31 #define APBC_PWM0 0xc macro
136 …{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
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| D | clk-pxa910.c | 29 #define APBC_PWM0 0xc macro
191 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa910_clk_init()
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| D | clk-of-mmp2.c | 38 #define APBC_PWM0 0x3c macro
160 …{MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lo…
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| D | clk-pxa168.c | 29 #define APBC_PWM0 0xc macro
186 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 36 #define APBC_PWM0 0x3c macro
235 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in mmp2_clk_init()
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| /linux-4.1.27/arch/arm/mach-mmp/ |
| D | clock-mmp2.c | 26 #define APBC_PWM0 APBC_REG(0x03c) macro
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